公开(公告)号：JP2005005706A

公开(公告)日：2005-01-06

申请号：JP2004167959

申请日：2004-06-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BARD KAREN A ,  DOBUZINSKY DAVID M ,  HO HERBERT L ,  KUMAR MAHENDAR ,  PENDLETON DENISE ,  STEIGERWALT MICHAEL D

IPC: H01L21/77 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66181 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/7841

Abstract: PROBLEM TO BE SOLVED: To enable the number of stored data bits per chip to be increased in an SOI type integrated circuit device including a DRAM array which is composed of DRAM cells equipped with a trench capacitor.
SOLUTION: When manufacturing the integrated circuit device, the DRAM array is formed in a SOI wafer having a uniform BOX layer 20 extending in the DPAM array. Thereby, (1) a collar oxide film forming process can be skipped, (2) a buried plate 105 can be connected to an ion implantation region 160 which extends through a device layer 30 and the BOX 20 and is connected to a conductive plug biased to the ground. On the other hand, a pass transistor is of a planer type NFET which is equipped with a leakage current electric discharge path connected to the ground through a grounded bit line and also equipped with a floating body.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了在包括由配备有沟槽电容器的DRAM单元组成的DRAM阵列的SOI型集成电路器件中使每芯片的存储数据位数增加。 解决方案：当制造集成电路器件时，DRAM阵列形成在具有在DPAM阵列中延伸的均匀BOX层20的SOI晶片中。 因此，可以跳过（1）环形氧化膜形成工艺，（2）掩埋板105可以连接到离子注入区域160，离子注入区域160延伸穿过器件层30和BOX 20并且连接到导电插塞偏置 到地面。 另一方面，传输晶体管是平面型NFET，其配备有通过接地位线连接到地并且还具有浮体的漏电流放电路径。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004015053A

公开(公告)日：2004-01-15

申请号：JP2003151411

申请日：2003-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  HO HERBERT L

IPC: H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10867 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To increase the degree of vertical separation between a passing wordline and a strap.
SOLUTION: If the thickness of an insulation layer is decreased in an SOI integrated circuit including a trench capacitor DRAM array, crosstalk is caused between a trench capacitor and the passing wordline 214 which passes over the trench capacitor. The buried strap on a capacitor center electrode 105 is enabled to come into contact with the backside of an SOI layer 60 by increasing the depth of a recess at the upper part of the trench and laterally undercutting the insulating layer, thereby increasing the degree of vertical separation between the passing wordline 214 and the strap.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JPH1074907A

公开(公告)日：1998-03-17

申请号：JP16576497

申请日：1997-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: A device layout has a device structure including a first device and a second device formed thereon, and an active region of the second region is located inside the upper surface so as to facilitate a three-dimensional device layout. SOLUTION: For example, a highly doped N polylayer is next formed on the surface. This polylayer is planarized up to an upper surface of a gate 895 to form a bit-line contact area 110. An MO dielectric layer is layed to expose the contact area 110. A metal layer 150 is next deposited so as to fill an contact opening 120. This metal layer 150 is etched for forming a bit-line conductor. The capacity of spatially positioning a device on a trench allows a more effective three-dimensional layout. As a result, the density of a device for a prescribed area can be increased.

公开(公告)号：JP2007150317A

公开(公告)日：2007-06-14

申请号：JP2006317746

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOBUZINSKY DAVID M ,  HO HERBERT L ,  MANDELMAN JACK A ,  OTANI YOICHI

IPC: H01L21/8247 ,  H01L21/265 ,  H01L21/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is formed in a semiconductor-on-insulator (SOI) substrate. SOLUTION: A memory cell comprises: a semiconductor-on-insulator substrate including a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer; and at least one vertical trench SONOS memory cell located in the semiconductor-on-insulator substrate. The at least one vertical trench SONOS memory cell comprises: a source diffusion located beneath the vertical trench; a selection gate channel located on one side of the vertical trench; an outward-diffused/Si-containing bridge located on and in contact with the selection gate channel; and a silicided doped region located adjacent to and in contact with an upper portion of the bridge. The bridge is present in the top semiconductor layer, the buried insulating layer, and the bottom semiconductor layer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元。 解决方案：存储单元包括：绝缘体上半导体衬底，包括通过掩埋绝缘层彼此分离的顶部半导体层和底部半导体层; 以及位于绝缘体上半导体衬底中的至少一个垂直沟道SONOS存储器单元。 所述至少一个垂直沟道SONOS存储单元包括：位于垂直沟槽下方的源极扩散; 位于所述垂直沟槽的一侧上的选择栅极沟道; 位于选择栅极通道上并与选择栅极通道接触的向外扩散/含Si桥; 以及位于与桥的上部相邻并与其接触的硅化物掺杂区域。 该桥存在于顶部半导体层，埋入绝缘层和底部半导体层中。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000012801A

公开(公告)日：2000-01-14

申请号：JP14714699

申请日：1999-05-26

Applicant: IBM ,  SIEMENS AG

Inventor： ECONOMIKOS LAERTIS ,  GRUENING ULRIKE ,  HO HERBERT L ,  RADENS CARL J ,  JAMMY RAGARAO ,  HOEPFNER JOACHIM ,  SHEN HUA

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned collar and a buried plate while forming a reliable node dielectrics on the collar without requiring a plurality of independent trench recesses for forming the buried plate and the collar. SOLUTION: Etching for a trench is made within a surface of a semiconductor substrate 10 and a dielectric material layer is formed on a side wall 12 of the trench. The dielectric material layer is partially eliminated to expose a lower base region of the upper part of the trench side wall 12. After that an oxide layer is made to grow on the upper part of the side wall 12. The dielectric layer is eliminated from a remaining part of the side wall 12 and a buried plate 17 is formed by doping. The dielectric layer includes the upper part of the collar and a node, (i,e, the trench wall at a portion of the buried plate 17) and is provided for the trench wall. An inner electrode 19 is formed at the inner part of the trench.

公开(公告)号：JPH11145415A

公开(公告)日：1999-05-28

申请号：JP24707098

申请日：1998-09-01

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  SHORT ALVIN P ,  STENGL REINHARD J ,  HO HERBERT L ,  POSCHENRIEDER BERNHARD ,  SRINIVASAN RADHIKA

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a second device of a transistor, for example, on first device of a trench, for example, in the manufacture of a dynamic random access memory using a three-dimensional trench capacitor. SOLUTION: A layer having an uppermost face of a single crystal is formed on a first device, and a layer 2 is used as a base for forming an active region of a second device. In this case, a substrate 305 having a single-crystal structure and the flat substrate surface is prepared, and a trench capacitor 315 is manufacture in the substrate. A polysilicon layer in the capacitor 315 is bored in the part lower than the substrate surface to form a recessed part, and an intermediate layer is formed in the recessed part to a height larger than the surface of a pad. This intermediate layer has the uppermost face of the single crystal. The surface of the intermediate layer and the pad are planarized in such a way that the uppermost surface of the intermediate layer substantially becomes flat to the substrate surface and a transistor 370 is manufactured on the uppermost face of the single crystal.

公开(公告)号：DE60141254D1

公开(公告)日：2010-03-25

申请号：DE60141254

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：AU2002241651A1

公开(公告)日：2002-07-24

申请号：AU2002241651

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WONG KWONG HON ,  LEE HYUN KOO ,  WANG YUN-YU ,  HO HERBERT L ,  HOINKIS MARK ,  BOETTCHER STEVEN H

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：DE69705443T2

公开(公告)日：2002-05-16

申请号：DE69705443

申请日：1997-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

公开(公告)号：DE69705443D1

公开(公告)日：2001-08-09

申请号：DE69705443

申请日：1997-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.