公开(公告)号：JP2000243213A

公开(公告)日：2000-09-08

申请号：JP2000046289

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WEBER STEFAN J ,  IGGULDEN ROY ,  NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL CHRISTOPH ,  HOINKIS MARK ,  VAN DEN BERG ROBERT

IPC: H01H85/00 ,  H01H69/02 ,  H01L21/82 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide a method for shrinking an area for a fuse to occupy on a semiconductor tip, and to adjust a fuse resistance relative to a fuse of a semiconductor device. SOLUTION: A fuse for a semiconductor is formed, so as to have a substrate 12 having a conductive passage disposed on its surface, a dielectric layer 14 disposed on the substrate, and a vertical fuse 110 vertically disposed on the surface. The vertical fuse penetrates through the dielectric layer 14 and is connected to the conductive passage. The vertical fuse also has a hole 108, a liner material is disposed on its vertical surface, and the fuse is cut off with fusing of the liner material along the vertical surface.

公开(公告)号：JP2000195860A

公开(公告)日：2000-07-14

申请号：JP37512499

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RONALD PHILLIPI ,  HOINKIS MARK ,  WEBER STEFAN ,  ROY IGARUDEN ,  WEIGAND PETER ,  LAWRENCE CLEVENGER

IPC: H01L23/52 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To increase the electromigration lifetime of a semiconductor device by stacking a liner by an ionizing metal plasma physical deposition method, thereby reducing the mass carriage by electromigration. SOLUTION: A dielectric layer is made on a substrate. The dielectric layer is patterned, and a contact hole 26 is made, and conductive material is stacked on a dielectric layer so as to fill the contact hole 26 and cover the dielectric layer. Next, excess material is removed by polishing from the surface 29 so as to make a flat surface for an additional layer. Next, a liner 40 is stacked on the dielectric layer 29. This liner consists of a material having high electromigration resistance. For example, titanium(Ti) and its alloy tantalum(Ta) and its alloy, or TiN or Tan is included as such a liner material. This liner 40 is stacked, using an ionizing metal plasma physical deposition method.

公开(公告)号：WO02056342A3

公开(公告)日：2004-01-08

申请号：PCT/US0149138

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，通过使用Ti的第一衬垫层（42），然后使用CVD的保形衬垫层（46），发现并解决了热处理后的开路问题 TiN，然后是TA或TaN的最终衬垫层（48），从而改善通孔和下面的铜层之间的粘附性，同时将由Ti和铜之间的合金化引起的电阻增加减少到可接受的量。

公开(公告)号：EP1356498A4

公开(公告)日：2009-05-13

申请号：EP01990114

申请日：2001-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ENGEL BRETT H ,  HOINKIS MARK ,  MILLER JOHN A ,  SEO SOON-CHEON ,  WANG YUN-YU ,  WONG HON WONG

IPC: H01K3/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/50 ,  H01L23/52 ,  H01L23/532 ,  H05K3/02

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect (30, 50) and low-k interlayer dielectrics (40), a problem of open circuits after heat treatment was discovered and solved bz the use of a first liner layer of Cr (42), followed by a conformal liner layer of CVD TiN (46), followed in turn bz a final liner layer of Ta or TaN (48), thus improving adhesion between the via (50) and the underlying copper layer (30) while maintianing low resistance.

公开(公告)号：EP1397830A4

公开(公告)日：2009-03-11

申请号：EP01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，发现热处理后开路的问题，并通过使用Ti的第一衬垫层（42），随后使用CVD共形衬垫层（46） TiN，然后依次是TA或TaN的最终衬垫层（48），因此改善了通孔和下面的铜层之间的粘合性，同时将由Ti和铜之间的合金化引起的电阻的增加减少到可接受的量。

公开(公告)号：DE60141254D1

公开(公告)日：2010-03-25

申请号：DE60141254

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：AT457081T

公开(公告)日：2010-02-15

申请号：AT01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN ,  HO HERBERT ,  HOINKIS MARK ,  LEE HYUN ,  WANG YUN-YU ,  WONG KWONG

IPC: C23C16/34 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/532

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：AU2002241651A1

公开(公告)日：2002-07-24

申请号：AU2002241651

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WONG KWONG HON ,  LEE HYUN KOO ,  WANG YUN-YU ,  HO HERBERT L ,  HOINKIS MARK ,  BOETTCHER STEVEN H

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：JPH11251420A

公开(公告)日：1999-09-17

申请号：JP36507798

申请日：1998-12-22

Applicant: SIEMENS AG ,  IBM

Inventor： HOINKIS MARK ,  RESTAINO DARRYL

IPC: B65G49/07 ,  B25J15/06 ,  H01L21/683 ,  H02N13/00 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To substantially prevent abrasions and scratches on the rear side of a wafer from becoming an excessive quantity during wafer processing. SOLUTION: When subsequent wafers 14 are processed subsequently on an electrostatic chuck, warpage of the wafer 14 is decided. The electrostatic chuck 12 clamps the wafer 14 on a clamping face by a clamping force. A controller detects the inherent warpage of the wafer 14 and decides on a minimum clamp voltage to be applied to the electrostatic chuck 12, based on the measured warpage. The voltage is a value decided for each wafer 14, so as to surely clamp the wafer 14 on the clamping face and to eliminate excessive warpage and abrasion on the rear side of the wafer 14. The data of the minimum clamp voltage and the related discriminating part for the wafer 14 for subsequent processing of each wafer 14 are decided and stored, by the use of the measured warpage.