公开(公告)号：CA1137641A

公开(公告)日：1982-12-14

申请号：CA349769

申请日：1980-04-14

Applicant: IBM

Inventor： HOMAN MERLE E ,  MACHOL GUENTHER K ,  WARREN LARRY M

IPC: G06F9/30 ,  G06F12/06 ,  G06F15/78 ,  G06F9/24

Abstract: A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An external instruction mode input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 external instruction (XI) input pins instead of from the on-chip ROS. A branch decision output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A wait output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state. SA9-78-071

公开(公告)号：FR2311355A1

公开(公告)日：1976-12-10

申请号：FR7610913

申请日：1976-04-09

Applicant: IBM

Inventor： CROSS JON L ,  HOMAN MERLE E ,  MACHOL GUENTHER K ,  MALM RICHARD L ,  SVELUND LARRY E

IPC: G06F7/00 ,  G06F11/00 ,  G06F13/00 ,  G06F13/42 ,  H04B10/00 ,  G06F3/04

公开(公告)号：CA911044A

公开(公告)日：1972-09-26

申请号：CA911044D

Applicant: IBM

Inventor： COCKE JOHN ,  FREIMAN CHARLES V ,  HOMAN MERLE E

IPC: G06F7/38 ,  G06F7/44 ,  G06F7/52

公开(公告)号：CA731802A

公开(公告)日：1966-04-05

申请号：CA731802D

Applicant: IBM

Inventor： HOMAN MERLE E

公开(公告)号：CA1199414A

公开(公告)日：1986-01-14

申请号：CA440032

申请日：1983-10-20

Applicant: IBM

Inventor： FISK DALE E ,  GRIFFITH ROBERT L ,  HOMAN MERLE E ,  RADIN GEORGE ,  RICHARDS WALDO J

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455 ,  G06F9/22 ,  G06F9/36

Abstract: If a predetermined field within a source instruction indexes and accesses a body of control information from memory, and if control information designates the field-to-field (register-to-register) mapping, then a skeleton target instruction can be filled in by either selectively copying the fieldsof the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instructions for a CPU of a second kind without disrupting the logical flow or execution of either source or target instruction streams.

公开(公告)号：CA1066812A

公开(公告)日：1979-11-20

申请号：CA252273

申请日：1976-05-11

Applicant: IBM

Inventor： CROSS JON L ,  HOMAN MERLE E ,  MACHOL GUENTHER K ,  MALM RICHARD L ,  SVELUND LARRY E

IPC: G06F7/00 ,  G06F11/00 ,  G06F13/00 ,  G06F13/42 ,  H04B10/00 ,  G06F9/16

Abstract: APPARATUS FOR CONTROL AND DATA TRANSFER BETWEEN A SERIAL DATA TRANSMISSION MEDIUM AND A PLURALITY OF DEVICES Apparatus under microprocessor control for use in communicating over a serial communication loop with a remote attached control unit. It is capable of establishing frame synchronization, interpreting commands, assembling data and transmitting bits on the loop. The apparatus also communicates with I/O devices over a demand/response interface. A microprocessor interface with the loop includes loop sync control which establishes bit synchronization and generates a restart pulse at bit receive time and bit send time. The execution of instructions by the microprocessor is stopped and the microprocessor enters a wait state when it has finished all previous work and is ready to receive a loop bit. When it is time to receive the loop bit the microprocessor is restarted in response to the restart pulse from the loop synchronization. or output operations to a device, the microprocessor loads the device address and a device command or data into shift registers and initiates the transfer by setting a latch. When the transfer to the device is completed, this latch is reset in response to a signal from the device.

公开(公告)号：CA1037599A

公开(公告)日：1978-08-29

申请号：CA223388

申请日：1975-03-25

Applicant: IBM

Inventor： FISK DALE E ,  HOMAN MERLE E

IPC: H04J3/00 ,  H03M7/00 ,  H04B14/02 ,  H04J3/06 ,  H04J3/16 ,  H04L5/22 ,  H04L25/49 ,  H04Q11/04

Abstract: TIME-DIVISION PULSE-MULTIPLEX DIGITAL ELECTRIC SIGNAL SWITCHING CIRCUIT ARRANGEMENT Bilevel or bistatic digital electric signals are transmitted directly through a time division multiplexing (TDM) switching component asynchronously of the TDM clocking pulse train. A pulse duration modulated(PDM) electric signal or like wave is converted to a pulse amplitude modulated (PDM) electric wave having aplitude and timing components indicating a predetermined relationship to the TDM sampling period. The input PDM wave is amplitude limited by conventional circuitry and phase relationship is indicated by a ramp wave generator or a digital counter with the slope of the ramp wave or the counting rate proportional to the sampling period. Other forms of analog-to-digital converter circuitry may be substituted. The converted PAM electric wave is then passed through the switching component in conventional manner. Thereafter, the switched PAM electric wave is analyzed for reconstructing the original PDM electric signal wave. Complementary circuitry us preferably used for regenerating the signal. The upper limit on the data rate corresponds to one transition of the input electric signal to one time division sampling period of the TDM switching component.

公开(公告)号：CA714195A

公开(公告)日：1965-07-20

申请号：CA714195D

Applicant: IBM

Inventor： HOMAN MERLE E