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公开(公告)号：US3691295A
公开(公告)日：1972-09-12
申请号：US3691295D
申请日：1970-03-31
Applicant: IBM
Inventor： FISK DALE E
IPC: H04L5/14
CPC classification number: H04L5/1423
Abstract: Transmission system for jointly linking a video source to a television display device, and a digital data source to a digital data output by means of a single coaxial cable. A video source and the digital data output are located at one end of the coaxial cable, with the television display device and digital data source located in the vicinity of the other end of the cable. Circuit arrangements are provided at the video source end of the cable, and also at the digital data source end of the cable, for respectively separating the video signal and the digital data signal from each other to thereby facilitate the transmission of video information in one direction through the coaxial cable while digital data is simultaneously transmitted through the cable in the other direction.
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公开(公告)号：CA878152A
公开(公告)日：1971-08-10
申请号：CA878152D
Applicant: IBM
Inventor： MARTIN HAROLD F , BROWN CAROLL J , CHESAREK DONALD J , FISK DALE E , REYNOLDS ZACK D , MA JOSEPH T
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Patent Agency Ranking
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公开(公告)号：CA1217869A
公开(公告)日：1987-02-10
申请号：CA469464
申请日：1984-12-06
Applicant: IBM
Inventor： FISK DALE E , PEREIRA LAWRENCE W , RADIN GEORGE
Abstract: INTERNAL BUS ARCHITECTURE FOR A PRIMITIVE INSTRUCTION SET MACHINE An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture of the internal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were architected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
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公开(公告)号：CA1035451A
公开(公告)日：1978-07-25
申请号：CA223596
申请日：1975-03-27
Applicant: IBM
Inventor： FISK DALE E , HOMAN MERLE E , MEILEY CHARLES L , REYNOLDS ZACK D , WATKINS ROBERT V , WIEDMER FRITZ S
Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.
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公开(公告)号：CA1199414A
公开(公告)日：1986-01-14
申请号：CA440032
申请日：1983-10-20
Applicant: IBM
Inventor： FISK DALE E , GRIFFITH ROBERT L , HOMAN MERLE E , RADIN GEORGE , RICHARDS WALDO J
Abstract: If a predetermined field within a source instruction indexes and accesses a body of control information from memory, and if control information designates the field-to-field (register-to-register) mapping, then a skeleton target instruction can be filled in by either selectively copying the fieldsof the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instructions for a CPU of a second kind without disrupting the logical flow or execution of either source or target instruction streams.
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公开(公告)号：CA1037599A
公开(公告)日：1978-08-29
申请号：CA223388
申请日：1975-03-25
Applicant: IBM
Inventor： FISK DALE E , HOMAN MERLE E
Abstract: TIME-DIVISION PULSE-MULTIPLEX DIGITAL ELECTRIC SIGNAL SWITCHING CIRCUIT ARRANGEMENT Bilevel or bistatic digital electric signals are transmitted directly through a time division multiplexing (TDM) switching component asynchronously of the TDM clocking pulse train. A pulse duration modulated(PDM) electric signal or like wave is converted to a pulse amplitude modulated (PDM) electric wave having aplitude and timing components indicating a predetermined relationship to the TDM sampling period. The input PDM wave is amplitude limited by conventional circuitry and phase relationship is indicated by a ramp wave generator or a digital counter with the slope of the ramp wave or the counting rate proportional to the sampling period. Other forms of analog-to-digital converter circuitry may be substituted. The converted PAM electric wave is then passed through the switching component in conventional manner. Thereafter, the switched PAM electric wave is analyzed for reconstructing the original PDM electric signal wave. Complementary circuitry us preferably used for regenerating the signal. The upper limit on the data rate corresponds to one transition of the input electric signal to one time division sampling period of the TDM switching component.
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