Abstract:
A statistically optimized data recovery apparatus in a system having data storage and retrieval means, said apparatus including error detection means, a plurality of error correction means, first schedulers for scheduling a plurality of error correction attempts, and a second scheduler and a parameter variation means, said second scheduler providing for ordered selection of the first scheduler, and said parameter variation means providing for variation of parameters of said retrieval means, in an attempt to recover data in error.
Abstract:
If a predetermined field within a source instruction indexes and accesses a body of control information from memory, and if control information designates the field-to-field (register-to-register) mapping, then a skeleton target instruction can be filled in by either selectively copying the fieldsof the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instructions for a CPU of a second kind without disrupting the logical flow or execution of either source or target instruction streams.