公开(公告)号：CA1014665A

公开(公告)日：1977-07-26

申请号：CA198452

申请日：1974-04-24

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HONG SE J ,  HSIAO MU-YUE ,  PATEL ARVIND M

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/19

Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.

公开(公告)号：DE2550342A1

公开(公告)日：1976-06-24

申请号：DE2550342

申请日：1975-11-08

Applicant: IBM

Inventor： HONG SE J ,  OSTAPKO DANIEL L

IPC: G06F11/22 ,  G01R31/3185 ,  G06F11/10 ,  H03K19/177 ,  G01R31/28

Abstract: 1475255 Selective signalling INTERNATIONAL BUSINESS MACHINES CORP 1 Oct 1975 [18 Dec 1974] 40080/75 Heading G4H A logic array with testing apparatus comprises a plurality of decoders feeding input lines of a logic-performing matrix, the matrix incorporating a check line intersecting the input lines for storing information on the number of operative logic means located along each of the input lines. In Fig. 1, input bits at 14 are decoded in pairs by decoders 12a, 12b ... 12, each decoder selecting one of a respective 4 row lines of an AND array 10. The array 10 has FETs at selected row-column intersections to provide on each column line the AND of a respective combination of the row lines. The column lines feed an OR array 24 which similarly has FETs at selected row-column intersections and feeds latches via its row lines. The AND array has an extra column line 21 specifying a parity bit for each row line according to the number of FETs which should be present in it, and the OR array has an extra row line 19 specifying a parity bit for each column line. To test the AND array, a command decoder 36 is used to enable the decoders 12a, 12b ... 12 in turn, each decoder, when enabled, being supplied with appropriate inputs to select all its outputs in turn. As each row line of the AND array is thus selected, the column outputs are loaded into a shift register 48 and parity-checked by an EXCL-OR tree 50. The OR array is then tested by decoupling the two arrays using a mask output 40 of the command decoder 36, and inserting a 1 into the shift register 48 and shifting it along thus selecting the column lines of the OR array in turn, the row outputs being parity-checked in each case by an EXCL-OR tree 54. Another output 42 of the command decoder 36 (used e.g. for normal operation) enables all the decoders 12a, 12b ... 12 and resets the shift register 48. EXCL-ORing may be done serially. Extra redundancy lines could be provided in the arrays.