公开(公告)号：JPH09180437A

公开(公告)日：1997-07-11

申请号：JP33365295

申请日：1995-12-21

Applicant: IBM

Inventor： SATO AKASHI ,  KATAYAMA YASUNAO

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To read or write data without any interruption at a constant or short access time regardless of, for example, the timing for reading, writing, or refreshing data in a DRAM. SOLUTION: When a request for reading or writing burst data is continuously inputted, a row decode(RD) and a column decode(CD) by a row decoder 42 and a column decoder 52, an array access(AR) and a recharge(PR) due to a data line driver 24, a bit switch 26, and a sense amplifier 28, and data transfer(TR) due to a write buffer 52 or a read buffer 54 are performed in parallel in pipeline system. When a timing for refreshing a DRAM array 22 arrives, a refresh address which is retained at a refresh controller 40 is outputted while burst data are being transferred and a series of refresh processing consisting of (RD), (AR), and (PR) are performed.

公开(公告)号：JPH0492287A

公开(公告)日：1992-03-25

申请号：JP20831690

申请日：1990-08-08

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  ROI EDOUIN SHIYUWARAIRE

IPC: G11C11/409 ,  G11C11/4091

Abstract: PURPOSE: To realize a DRAM capable of high speed operation by limiting a downward voltage swing of a low level side bit line to a prescribed voltage level higher than a reference voltage. CONSTITUTION: The downward voltage swing of the low level side bit line BLN generating by the activation of a first latch 10 is made to clamp to a prescribed bit line voltage level by controlling the voltage of a common node N1 of the first latch 10. And when FETs TN5, TN6 are continued to conduct, the voltage of the low level side bit line is dropped to about zero V. Hear, when the voltage of the low level side bit line BLN is dropped to a prescribed bit line low voltage level VBLL corresponding to a low level restore voltage by the activation of the latch 10, a PS1 and PS2 become low to turn off the TN5 and TN6. Therefore, the low level restore voltage is automatically provided to the low level side bit line.

公开(公告)号：JP2013114397A

公开(公告)日：2013-06-10

申请号：JP2011259178

申请日：2011-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： TAKANO KOJI ,  OBA NOBUYUKI ,  KATAYAMA YASUNAO

IPC: G06F13/10 ,  G06F12/00

CPC classification number: G06F17/30132

Abstract: PROBLEM TO BE SOLVED: To make control of a receiver and downloading possible by avoiding a problem of a cache by an OS.SOLUTION: A mirror file number corresponding to a file to be requested is transmitted to a host OS. It is determined that whether or not data is cached in the host OS, and a block device is requested to read data of the mirror file number when it is determined that the transmitted data of the mirror file number is not cached. The block device acquires an address in memory in which actual content corresponding to a sector number is stored, acquires a sequence number corresponding to the content, changes the acquired sequence number and read data in the acquired address in the memory. Data obtained by adding the changed sequence number to the read data is provided to the host OS. When it is determined that data is cached in the host OS, the data cached in the host OS is provided.

Abstract translation: 要解决的问题：通过避免OS的高速缓存问题，来使接收机的控制和下载成为可能。 解决方案：将与要请求的文件相对应的镜像文件号码发送到主机OS。 确定数据是否被缓存在主机OS中，并且当确定镜像文件号的发送数据未被高速缓存时，请求块装置读取镜像文件号的数据。 块装置获取存储有对应于扇区号的实际内容的存储器中的地址，获取与内容相对应的序列号，改变所获取的序列号并读取存储器中获取的地址中的数据。 通过将改变的序列号添加到读取的数据而获得的数据被提供给主机OS。 当确定在主机OS中缓存数据时，提供缓存在主机OS中的数据。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011129981A

公开(公告)日：2011-06-30

申请号：JP2009283872

申请日：2009-12-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YAMANE TOSHI ,  KATAYAMA YASUNAO

IPC: H03M13/45 ,  H03M13/19

CPC classification number: H03M13/112 ,  H03M13/2957 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6583

Abstract: PROBLEM TO BE SOLVED: To achieve a decoding technique (approximate decoding technique) of achieving stable operation even if noise variance is low at the implementation with a fixed fractional part arithmetic operation having a finite dynamic range.
SOLUTION: A computer executes calculation using a sum-product decoding method (belief propagation method) with respect to (LDPC or turbo) codes. For calculating an update equation of a log extrinsic value ratio from an input, a (separated) correction term is prepared obtained by variable transformation (scale transformation) of the update equation so that the update equation is represented by a sum (combination) of a plurality of terms by transformation of the equation and a communication channel noise variance is a term separated from other terms constituting a sum of a plurality of terms as a term to be a factor (scale factor) by which a log is multiplied. With an estimated communication channel noise variance as an input, the (separated) correction term is approximated by a simple function so as to cause the computer to make calculation (iteration) on the basis of a fixed fractional part on bit strings of finite length.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：即使在具有有限动态范围的固定分数算术运算的实施中，即使在实现噪声方差较小的情况下，也可以实现实现稳定运算的解码技术（近似解码技术）。 解决方案：计算机使用关于（LDPC或turbo）码的和乘解码方法（置信传播方法）来执行计算。 为了从输入计算对数外在值比的更新方程，通过更新方程的变换（缩放变换）获得的（分离的）校正项被准备，使得更新方程由 通过方程的变换和通信信道噪声方差的多个项是与构成多个项的和的其他项分离的项，作为要乘以对数的因子（比例因子）的项。 利用估计的通信信道噪声方差作为输入，（分离）校正项由简单函数近似，以使计算机基于有限长度的位串上的固定小数部分进行计算（迭代）。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008016907A

公开(公告)日：2008-01-24

申请号：JP2006182985

申请日：2006-07-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KATAYAMA YASUNAO ,  NAKANO DAIKI

IPC: H03M13/29

CPC classification number: H03M13/2906 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/373

Abstract: PROBLEM TO BE SOLVED: To improve a recovery rate of packets while efficiently utilizing optimum quantity of redundant information.
SOLUTION: A Partially-Overlapped Block (POB) code as a new encoding system is disclosed in which a plurality of different block codes are combined so that they partially overlap one another. A decoding method is also disclosed corresponding to this encoding system. Further, a method is disclosed for recovering a plurality of packets using a loss correction capability of this code. According to this technique, recovery of the larger number of packets than the number of added redundant packets per frame can be possible by well reusing redundant information of neighboring frames without increasing the asymptotic calculation quantity of a decoding algorithm.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提高数据包的恢复速率，同时有效利用最佳数量的冗余信息。 解决方案：公开了作为新的编码系统的部分重叠块（POB）代码，其中组合多个不同的块代码，使得它们部分地彼此重叠。 对应于该编码系统也公开了解码方法。 此外，公开了一种使用该代码的损失校正能力来恢复多个分组的方法。 根据该技术，通过在不增加解码算法的渐近计算量的情况下，重复使用相邻帧的冗余信息，可以恢复比每帧增加的冗余分组数更大数量的分组。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007104460A

公开(公告)日：2007-04-19

申请号：JP2005293310

申请日：2005-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KATAYAMA YASUNAO

IPC: H04L1/00 ,  G06F11/10

Abstract: PROBLEM TO BE SOLVED: To achieve interconnect communication mounting an error-correcting function without affecting latency when there occurs no error in a reception apparatus (600) that transfers an output from a transmission apparatus (500) through an external communication path (530) to a next-stage processing circuit (700) connected to the next stage. SOLUTION: The reception apparatus comprises: a circuit (610) for receiving an input of a reception packet and detecting a portion corresponding to a header; an Invalidation generation circuit (623) which decodes the reception packet, performs error detection and generates an Invalidation signal if any error is detected; a decoding circuit (620) including a buffer (621) capable of holding that reception packet just for a time required for error correction; and an output selection circuit (630) for selecting, using the Invalidation signal, whether to turn the reception packet into a state of speculatively transferring the reception packet to a next-stage processing circuit on the next stage while keeping it as it is without ending reception of the reception packet, or to turn the reception packet into a state of transferring the reception packet after decoding. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了实现在通过外部通信路径传送来自发送装置（500）的输出的接收装置（600）中没有发生错误的情况下，实现不影响等待时间的互连通信的安装纠错功能 530）连接到下一级处理电路（700）。 解决方案：接收装置包括：电路（610），用于接收接收分组的输入并检测对应于报头的部分; 对接收分组进行解码的无效生成电路（623），如果检测到任何错误，则执行错误检测并产生无效信号; 一个解码电路（620），包括一个缓冲器（621），该缓冲器能够保持该接收分组刚刚达到纠错所需的时间; 以及输出选择电路（630），用于使用无效信号来选择是否将接收分组转换成下一级的下一级处理电路的推测性传送的状态，同时保持原样接收 接收分组，或者将解码后的接收分组转换为接收分组的状态。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004040199A

公开(公告)日：2004-02-05

申请号：JP2002190742

申请日：2002-06-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KATAYAMA YASUNAO ,  YAMANE TOSHIYUKI

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/15 ,  H03M13/29

CPC classification number: G11B20/1833 ,  H03M13/2906

Abstract: PROBLEM TO BE SOLVED: To provide a communication apparatus and the like, capable of appropriately communicating by correcting errors in communication due to noises generated on a transmission line and the like. SOLUTION: An encoder, for adding error-correcting codes to an input data sequence, is provided with a first code adding unit for adding binary error-correcting codes to each of a plurality of first data blocks, obtained by dividing the input data sequence; and a second code adding unit for adding symbol error-correcting codes for performing error correction by symbol units, having a predetermined length to each of second data blocks obtained, by dividing the input data sequence in a form different from that of the plurality of first data blocks. The number of bit errors per total bit number in the first data blocks, to which the binary error-correcting codes are added, which can be corrected by the binary error-correcting codes, is larger than the number of bit errors per total bit number in the second data blocks, to which the symbol error-correcting codes are added, which can be corrected by the symbol error-correcting codes . COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002335167A

公开(公告)日：2002-11-22

申请号：JP2001196223

申请日：2001-06-28

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  MORIOKA SUMIO ,  YAMANE TOSHIYUKI

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/27 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To provide a decoding circuit, a decoder with the decoding circuit, a decoding method, and a semiconductor device. SOLUTION: The decoding circuit for correcting an error in digital signal is composed of an input unit 10 for receiving an input digital encoded signal ID in parallel corresponding to code interleaving; a processing unit 12, including an error-position polynomial coefficient processing unit 18 and an error-value polynomial coefficient processing unit 20 for processing each data output in serial among interleaved encoded words from the input unit 10; and an output unit 14 for receiving the output of the processing unit 12 and the input digital signal ID, and generating an output digital signal OD, in parallel corresponding to the code interleaving, after the error is corrected in a linear processing in the Galois field from the output of processing unit 12 and the input digital signal.

公开(公告)号：JP2000307435A

公开(公告)日：2000-11-02

申请号：JP9864799

申请日：1999-04-06

Applicant: IBM

Inventor： MORIOKA SUMIO ,  KATAYAMA YASUNAO

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To reduce the overall circuit scale by allowing a plurality of coding circuits having different maximum error correction capability to share most of circuit components in common. SOLUTION: In the case that a received message is an information word, an attachment circuit 10 attaches a fixed value to the information word. Then a linear arithmetic circuit 11 receives data resulting from attaching the fixed value to this information word, or data of the received message when it is a received word, or data resulting from adding a prescribed fixed value to a received word, if required, to make number of bits of the data given to the linear arithmetic circuit constant, and applies a linear arithmetic operation to the received data by using a prescribed matrix to calculate an intermediate signal (u). The bit length of the intermediate signal (u) is smaller than that of a corrected word given to the linear arithmetic circuit 11. That is, number of circuits can remarkably be reduced by using the intermediate signal (u) with the smaller bit length so as to obtain a parity value or the like without using the information word and the received word that are directly received for the parity calculation and the syndrome calculation.

公开(公告)号：JP2012170014A

公开(公告)日：2012-09-06

申请号：JP2011031231

申请日：2011-02-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBA NOBUYUKI ,  TAKANO KOJI ,  KATAYAMA YASUNAO

IPC: H04W28/04 ,  H04L29/08

CPC classification number: H04L1/1854 ,  H04L1/1838 ,  H04L1/24 ,  H04W28/04

Abstract: PROBLEM TO BE SOLVED: To download data of a high-capacity file from a server (an access point) to a client (a portable device) of a user at a high speed with efficiently using both millimeter wave wireless communication and the conventional wireless communication (WiFi, Bluetooth (R), 3G, and the like).SOLUTION: File data is packetized and transmitted from a server to a client. The file data is transmitted as a data packet by a millimeter wave. In parallel to that, a check-out packet (a roll-calling packet) corresponding to the data packet is transmitted. At establishment of a link, a latency of each communication channel is measured for testing. On a reception side, when reception of the check-out packet is completed, whether or not a millimeter wave packet corresponding to the check-out packet is arrived is checked (or roll-calling is performed). If no corresponding millimeter wave packet is arrived, it is determined that the corresponding millimeter wave packet is lost, and a retransmission request is returned to the server readily via WiFi.

Abstract translation: 要解决的问题：为了将高容量文件从服务器（接入点）的数据高速地下载到用户的客户机（便携式设备），有效地使用毫米波无线通信和 传统的无线通信（WiFi，蓝牙，3G等）。 解决方案：文件数据被打包并从服务器发送到客户端。 文件数据以毫米波作为数据包发送。 与此并行地，发送对应于数据分组的检出分组（滚动呼叫分组）。 在建立链路时，测量每个通信信道的延迟。 在接收侧，当接收到检出包完成时，检查与检出包相对应的毫米波分组是否被到达（或进行滚动呼叫）。 如果没有相应的毫米波分组到达，则确定对应的毫米波分组丢失，并且通过WiFi容易地将重传请求返回给服务器。 版权所有（C）2012，JPO＆INPIT