公开(公告)号：GB2403321A

公开(公告)日：2004-12-29

申请号：GB0423215

申请日：2003-04-01

Applicant: IBM

Inventor： LEE VAN HOA ,  WILLOUGHBY DAVID

IPC: G06F20060101 ,  G06F9/40 ,  G06F9/46 ,  G06F9/50 ,  G06F15/177

Abstract: A method, apparatus, and computer instructions for managing a set of processors. In response to a request to deallocate a processor assigned to a partition within the logical partitioned data processing system, the processor in the set of processors, is stopped. In response to stopping the processor, the processor is placed in an isolated state in which the processor is isolated from the partition. The processor is then placed in a pool of resources for later reassignment.

公开(公告)号：CA2441799A1

公开(公告)日：2002-10-24

申请号：CA2441799

申请日：2002-03-21

Applicant: IBM

Inventor： LEE VAN HOA ,  TRAN KIET ANH

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/40

Abstract: A method, apparatus and program for booting a non-uniform-memory-access (NUM A) machine are provided. The invention comprises configuring a plurality of standalone, symmetrical multiprocessing (SMP) systems to operate within a NU MA system. A master processor is selected within each SMP; the other processors in the SMP are designated as NUMA slave processors. A NUMA master processor is then chosen from the SMP master processors; the other SMP master processors are designated as NUMA slave processors. A unique NUMA ID is assigned to eac h SMP that will be part of the NUMA system. The SMPs are then booted in NUMA mode in one-pass with memory coherency established right at the beginning of the execution of the system firmware.

公开(公告)号：CA2437600A1

公开(公告)日：2002-09-19

申请号：CA2437600

申请日：2002-01-26

Applicant: IBM

Inventor： FOSTER ROBERT K ,  LEE VAN HOA ,  SMITH TIMOTHY A ,  WILLBOUGHBY DAVID R

IPC: G06F9/445 ,  G06F9/46 ,  G06F9/50 ,  G06F9/00

Abstract: A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running independently from the other logical partitions. The system also includes a console coupled to the comput er system for accepting logical partition configuration data input by an operator. The configuration data entered by the operator specifies the processors, I/O, and memory allocated to each logical partition defined for the system. The system further includes a set of tables maintained in the nonvolatile memory for storing the logical partition configuration data, suc h that the logical partition configuration data is persistent across system power cycles.

公开(公告)号：DE10045410A1

公开(公告)日：2001-04-26

申请号：DE10045410

申请日：2000-09-14

Applicant: IBM

Inventor： HARTMANN STEVEN PAUL ,  LEE VAN HOA ,  MILLER II MILTON DEVON

IPC: G06F12/08

Abstract: The cache with one entry is invalidated by loading preset data value representing invalid instruction into the cache line. The invalidated cache line is restored, in response to a recovery instruction. Independent claims are also included for the following: (a) Data processor; (b) Computer program product

公开(公告)号：CA2231387A1

公开(公告)日：1998-10-04

申请号：CA2231387

申请日：1998-03-09

Applicant: IBM

Inventor： LEE VAN HOA

IPC: G06F9/46 ,  G06F15/177

Abstract: One aspect of the invention relates to a method useful in a multiprocessor syste m for operating a processor. In one version of the invention, the method includes the steps of storing halt signature data in a register on the processor, the halt signatur e data being representative of whether the processor is in a halt state, storing start addres s data in memory which is accessible by the processor, executing an interruptible spin loo p with the processor, and comparing the halt signature data with a predetermined halt signa ture to determine whether the processor is in a halt state when an interrupt is received and reading the start address data from memory to determine whether there is a reque st to start if the processor is in a halt state.