公开(公告)号：WO02073396A2

公开(公告)日：2002-09-19

申请号：PCT/EP0200820

申请日：2002-01-26

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： FOSTER ROBERT K ,  LEE VAN HOA ,  SMITH TIMOTHY A ,  WILLBOUGHBY DAVID R

IPC: G06F9/445 ,  G06F9/46 ,  G06F9/50 ,  G06F9/00

CPC classification number: G06F9/5016 ,  G06F9/4401

Abstract: A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running independently from the other logical partitions. The system also includes a console coupled to the computer system for accepting logical partition configuration data input by an operator. The configuration data entered by the operator specifies the processors, I/O, and memory allocated to each logical partition defined for the system. The system further includes a set of tables maintained in the nonvolatile memory for storing the logical partition configuration data, such that the logical partition configuration data is persistent across system power cycles.

Abstract translation: 公开了一种用于管理分区配置数据的逻辑分区（LPAR）计算机系统，其包括非易失性存储器和多个逻辑分区，每个逻辑分区独立于其他逻辑分区运行。 该系统还包括耦合到计算机系统的控制台，用于接受由操作员输入的逻辑分区配置数据。 由操作员输入的配置数据指定为系统定义的每个逻辑分区分配的处理器，I / O和内存。 该系统还包括一组保存在非易失性存储器中用于存储逻辑分区配置数据的表，使得逻辑分区配置数据在系统电源周期之间是持续的。

公开(公告)号：JP2002304364A

公开(公告)日：2002-10-18

申请号：JP2002042190

申请日：2002-02-19

Applicant: IBM

Inventor： DAWKINS GEORGE JOHN ,  LEE VAN HOA ,  RANDALL DAVID LEE ,  TRAN KIET ANH

IPC: G06F13/14 ,  G06F13/28

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for implementing logical partition of an input/output slot in a data processing system, and a computer.program product. SOLUTION: In one form of implementation, this system includes a hypervisor and at least one DMA address inspecting component. The hypervisor receives an indirect memory.access demand regarding access to an input/output slot, and prohibits a device in a certain logical section from accessing to an input/ output slot assigned to a different logical section. The DMA address inspecting component receives a direct memory.access demand, and prohibits completion of a demand regarding an address which is not in the same logical section for the device of a requester. A demand regarding an address corresponding to the same logical section for the device of the requester is placed in a primary PCI bus by the DMA address inspecting component for transmission of a system.memory.

公开(公告)号：JP2002268900A

公开(公告)日：2002-09-20

申请号：JP2002049020

申请日：2002-02-26

Applicant: IBM

Inventor： LEE VAN HOA ,  NULU SAYILEELA

IPC: G06F11/00 ,  G06F9/445 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for managing system firmware in a data processing system provided with a plurality of logical partitions. SOLUTION: It is judged whether the first logical partition within the plurality of partitions is present in the data processing system or not in response to the reception of a request for updating the system firmware from the first logical partition within the plurality of logical partitions in the data processing system. The system firmware is updated from the first logical partition in the data processing system in response to the judgement that the first logical partition within the plurality of logical partitions is present in the data processing system. Then starting of an additional partition within the plurality of logical partitions in the data processing system is prohibited till the firmware update from the first logical partition is completed.

公开(公告)号：JP2007133901A

公开(公告)日：2007-05-31

申请号：JP2007001945

申请日：2007-01-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEE VAN HOA ,  NULU SAYILEELA

IPC: G06F9/46 ,  G06F11/00 ,  G06F9/445

CPC classification number: G06F8/65

Abstract: PROBLEM TO BE SOLVED: To provide a method for managing system firmware in a data processing system having a plurality of logical partitions.
SOLUTION: Responding to a request to update the system firmware from a first logical partition within the plurality of logical partitions in the data processing system, a determination is made whether the first logical partition within the plurality of logical partitions is present in the data processing system. Responding to the determination that the first logical partition within the plurality of logical partitions is present in the data processing system, the system firmware is updated from the first logical partition in the data processing system. Then, starting of additional partitions within the plurality of logical partitions in the data processing system is inhibited, until the firmware update from the first logical partition is complete.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在具有多个逻辑分区的数据处理系统中管理系统固件的方法。 解决方案：响应于在数据处理系统中的多个逻辑分区内的第一逻辑分区更新系统固件的请求，确定多个逻辑分区中的第一逻辑分区是否存在于 数据处理系统。 响应于数据处理系统中存在多个逻辑分区内的第一逻辑分区的确定，从数据处理系统中的第一逻辑分区更新系统固件。 然后，禁止在数据处理系统的多个逻辑分区内开始额外的分区，直到来自第一逻辑分区的固件更新完成。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005293574A

公开(公告)日：2005-10-20

申请号：JP2005076077

申请日：2005-03-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEE VAN HOA

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/14

CPC classification number: G06F12/0292 ,  G06F12/10

Abstract: PROBLEM TO BE SOLVED: To support a system memory address with holes.
SOLUTION: A first logical address area is produced by virtualizing a first physical address area allocated for a system memory of an operating system operated by a processor configured to support logical partitions. A second logical address area is produced by virtualizing a second physical address area. The first and second physical address areas are discontinuous. The first and second physical address areas are visualized so that the first logic address area and the second logic address area continue. A third logical address area is produced by virtualizing memory mapped input/output physical address area which exists between the first physical address area and the second physical address area. A lowest logical address of the third logical address area exceeds a respective uppermost part logical address of the first and second logical address areas.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：支持带有孔的系统内存地址。 解决方案：通过虚拟化分配给由配置为支持逻辑分区的处理器操作的操作系统的系统存储器的第一物理地址区域来产生第一逻辑地址区域。 通过虚拟化第二物理地址区域来产生第二逻辑地址区域。 第一和第二物理地址区域是不连续的。 可视化第一和第二物理地址区域，使得第一逻辑地址区域和第二逻辑地址区域继续。 通过虚拟存在于第一物理地址区域和第二物理地址区域之间的存储器映射的输入/输出物理地址区域来产生第三逻辑地址区域。 第三逻辑地址区域的最低逻辑地址超过第一和第二逻辑地址区域的相应最上部逻辑地址。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：AT305152T

公开(公告)日：2005-10-15

申请号：AT02701434

申请日：2002-02-27

Applicant: IBM

Inventor： DAWKINS GEORGE JOHN JR ,  LEE VAN HOA ,  PATEL KANISHA ,  PHAN PETER DINH ,  INTELL PROPERT LAW ,  WILLOUGHBY DAVID

IPC: G06F9/46 ,  G06F9/445 ,  G06F9/455

Abstract: A method, apparatus, and computer implemented instructions for controlling power in a data processing system having a plurality of logical partitions. Responsive to receiving a request to turn off the power for a logical partition within the plurality of logical partitions in the data processing system, a determination is made as to whether an additional partition within the plurality of logical partitions is present in the data processing system. The power is turned off in the data processing system in response to a determination an additional partition within the plurality of logical partitions is absent in the data processing system. The logical partition is shut down in response to a determination that an additional partition within the plurality of logical partitions is present in the data processing system. The mechanism of the present invention also provides for rebooting logical partitions. A request is received to reboot a logical partition within the plurality of logical partitions. A reset signal is activated only for each processor assigned to the logical partition.

公开(公告)号：CA2439609A1

公开(公告)日：2002-09-12

申请号：CA2439609

申请日：2002-02-27

Applicant: IBM

Inventor： DAWKINS GEORGE JOHN JR ,  PHAN PETER DINH ,  WILLOUGHBY DAVID R ,  LEE VAN HOA ,  PATEL KANISHA

IPC: G06F9/46 ,  G06F9/445 ,  G06F9/455

Abstract: A method, apparatus, and computer implemented instructions for controlling power in a data processing system having a plurality of logical partitions. Responsive to receiving a request to turn off the power for a logical partition within the plurality of logical partitions in the data processing system, a determination is made as to whether an additional partition within the plurality of logical partitions is present in the data processing system . The power is turned off in the data processing system in response to a determination an additional partition within the plurality of logical partitions is absent in the data processing system. The logical partition is shut down in response to a determination that an additional partition within the plurality of logical partitions is present in the data processing system . The mechanism of the present invention also provides for rebooting logical partitions. A request is received to reboot a logical partition within the plurality of logical partitions. A reset signal is activated only for each processor assigned to the logical partition.

公开(公告)号：AT330277T

公开(公告)日：2006-07-15

申请号：AT02708495

申请日：2002-03-21

Applicant: IBM

Inventor： LEE VAN HOA ,  TRAN KIET ANH

IPC: G06F15/177 ,  G06F9/445

公开(公告)号：CA2482034A1

公开(公告)日：2003-11-20

申请号：CA2482034

申请日：2003-04-01

Applicant: IBM

Inventor： LEE VAN HOA ,  WILLOUGHBY DAVID

IPC: G06F20060101 ,  G06F9/40 ,  G06F9/46 ,  G06F9/50 ,  G06F15/177

Abstract: A method, apparatus, and computer instructions for managing a set of processors. In response to a request to deallocate a processor assigned to a partition within the logical partitioned data processing system, the process or in the set of processors, is stopped. In response to stopping the processor, the processor is placed in an isolated state in which the processor is isolated from the partition. The processor is then placed in a pool of resources for later reassignment.

公开(公告)号：DE10045410B4

公开(公告)日：2006-08-10

申请号：DE10045410

申请日：2000-09-14

Applicant: IBM

Inventor： HARTMANN STEVEN PAUL ,  LEE VAN HOA ,  MILLER II MILTON DEVON

IPC: G06F12/08

Abstract: A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.