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公开(公告)号：DE2817183A1
公开(公告)日：1978-11-09
申请号：DE2817183
申请日：1978-04-20
Applicant: IBM
IPC: G06F13/12 , G06F7/00 , G06F9/38 , G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177 , G06F9/18 , G06F13/06
Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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Patent Agency Ranking
公开(公告)号：IT1209221B
公开(公告)日：1989-07-16
申请号：IT2199380
申请日：1980-05-13
Applicant: IBM
Inventor： FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
Abstract: A storage address link register system for enabling nested program branching wherein a first subroutine may call a second subroutine which is executed before the first subroutine returns program control back to the program which called it. The system includes a mechanism whereby the same set of storage address link registers may be used for nested branching both during the execution of a normal program and during the execution of an interrupt service program which breaks into the normal program and takes over control of the processor for a short interval of time. A mechanism is provided for saving the normal program values in the link registers at the commencement of the interrupt service program. A further mechanism is provided for monitoring the usage of the link registers by the interrupt program for enabling the normal program values to be restored in the link registers only after all interrupt program values have been removed from such link registers.
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公开(公告)号：DE2965985D1
公开(公告)日：1983-09-01
申请号：DE2965985
申请日：1979-06-01
Applicant: IBM
Inventor： DIXON JERRY DUANE , LEININGER JOEL CALVIN
IPC: G06F12/06 , G06F9/32 , G06F9/34 , G06F9/355 , G06F9/40 , G06F12/02 , G06F9/36 , G06F13/00 , G11C8/00
Abstract: In a data processing system, a mechanism provides independent assignment of page locations for a program's instructions and its data and better enables control to be transferred between programs, or portions thereof, that reside at different addresses in different pages of a multiple page instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return and Link instructions, each of which transfers control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.
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公开(公告)号：AU525348B2
公开(公告)日：1982-11-04
申请号：AU4679379
申请日：1979-05-08
Applicant: IBM
Inventor： FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
Abstract: A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.
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公开(公告)号：IT8021993D0
公开(公告)日：1980-05-13
申请号：IT2199380
申请日：1980-05-13
Applicant: IBM
Inventor： FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
Abstract: A storage address link register system for enabling nested program branching wherein a first subroutine may call a second subroutine which is executed before the first subroutine returns program control back to the program which called it. The system includes a mechanism whereby the same set of storage address link registers may be used for nested branching both during the execution of a normal program and during the execution of an interrupt service program which breaks into the normal program and takes over control of the processor for a short interval of time. A mechanism is provided for saving the normal program values in the link registers at the commencement of the interrupt service program. A further mechanism is provided for monitoring the usage of the link registers by the interrupt program for enabling the normal program values to be restored in the link registers only after all interrupt program values have been removed from such link registers.
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公开(公告)号：DE2816711A1
公开(公告)日：1978-11-02
申请号：DE2816711
申请日：1978-04-18
Applicant: IBM
Inventor： BIRNEY RICHARD EUGENE , LEININGER JOEL CALVIN , TAYLOR GEORGE PHILLIPS
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