公开(公告)号：DE3785961T2

公开(公告)日：1993-12-23

申请号：DE3785961

申请日：1987-01-13

Applicant: IBM

Inventor： HUFFMAN DAVID RICHARD ,  LEWIS SCOTT CLARENCE ,  ROCK JAMES EDWARD

IPC: G11C11/56 ,  G11C27/02 ,  G11C7/00

Abstract: An improved sense circuit for determining the data state of a memory cell in a multilevel storage system includes at least two differential voltage level sensing circuits (13, 14). A first differential voltage level sensing circuit (13) compares the relative magnitudes of a data input signal voltage level corresponding to a particular memory cell (11 or 12) charge level and a first reference voltage level, thereby providing at least one first binary data output signal (D1). The first binary data output signal is then used to generate a second reference voltage level having a magnitude different from that of the first reference voltage level. A second differential voltage sensing level circuit (14) compares the relative magnitudes of an adjusted data input signal voltage level and a second reference voltage level, thereby providing at least one second binary data output signal (D2). The adjusted data input signal corresponds to a function of the first data input signal. Hence, the binary data output signals provided correspond to the charge level stored in the memory cell.

公开(公告)号：AU6232790A

公开(公告)日：1991-04-18

申请号：AU6232790

申请日：1990-09-10

Applicant: IBM

Inventor： DRAKE CHARLES EDWARD ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/0175

Abstract: A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：DE3275619D1

公开(公告)日：1987-04-09

申请号：DE3275619

申请日：1982-12-20

Applicant: IBM

Inventor： LEWIS SCOTT CLARENCE

IPC: H03K5/13 ,  G05F1/46 ,  G05F3/24 ,  H03K3/02 ,  H03K5/15

Abstract: A signal generating circuit for an integrated circuit device responsive to first (CS) and second (DATA IN) externally applied input signals occurring at a predetermined time interval In which the performance of a first input signal responsive circuit (12) is made to vary inversely with respect to the performance of other internal signal generating circuits (10,18, TC) such that internally generated signals will occur at a predetermined time with respect to the external input signals regardless of the influence of variable parameters. Power dissipation of the first input signal responsive circuit also varies inversely with respect to that of other circuits present on the integrated circuit device so that total power dissipation is minimized.

公开(公告)号：DE2246756A1

公开(公告)日：1973-05-17

申请号：DE2246756

申请日：1972-09-23

Applicant: IBM

Inventor： BLOUNT FREDERICK THOMAS ,  GELLER HENRY ANDREW ,  LEWIS SCOTT CLARENCE ,  MOORE RICHARD DAVID ,  REDMOND JOSEPH MASON ,  LEUNG HOWARD

IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C11/416 ,  H03K3/288 ,  H03K17/62 ,  G11C7/00