公开(公告)号：BR9200054A

公开(公告)日：1992-09-08

申请号：BR9200054

申请日：1992-01-10

Applicant: IBM

Inventor： COMPORT STEVEN T ,  LIPTAY JOHN S ,  WEEB CHARLES F

IPC: G06F9/38 ,  G06F9/00 ,  G06F11/28

Abstract: A system and method whereby a central processor can continue operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system and method, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that the interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and all of the processing was done in a single instant at the moment that the fetches became allowed.

公开(公告)号：BR9200006A

公开(公告)日：1992-09-08

申请号：BR9200006

申请日：1992-01-02

Applicant: IBM

Inventor： BERSTICK VIKTORS ,  LIPTAY JOHN S ,  PEDERSEN RAYMOND JAMES

IPC: G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F7/10

公开(公告)号：CA2056715A1

公开(公告)日：1992-07-17

申请号：CA2056715

申请日：1991-11-29

Applicant: IBM

Inventor： COMFORT STEVEN T ,  LIPTAY JOHN S ,  WEBB CHARLES F

IPC: G06F9/38 ,  G06F9/46 ,  G06F15/16 ,  G06F9/30

Abstract: PO9-90-028 OVERLAPPED SERIALIZATION A system and method whereby a central processor can continue operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system and method, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that the interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and all of the processing was done in a single instant at the moment that the fetches became allowed.

公开(公告)号：FR2423822A1

公开(公告)日：1979-11-16

申请号：FR7905120

申请日：1979-02-22

Applicant: IBM

Inventor： GANNON PATRICK M ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W

IPC: C08F4/46 ,  G06F9/308 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0886 ,  G06F9/06 ,  G11C9/06

公开(公告)号：CA986230A

公开(公告)日：1976-03-23

申请号：CA180753

申请日：1973-09-11

Applicant: IBM

Inventor： AHEARN THOMAS P ,  CHRISTENSEN NEAL T ,  GANNON PATRICK M ,  LEE ARLIN E ,  LIPTAY JOHN S ,  CAPOWSKI ROBERT S

IPC: G06F12/10

Abstract: This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same addresses over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. Each translation retained by the DLAT is identified by an identifier (ID) that signifies the set of tables used in that translation. This identifier is compared with an identifier generated for the currently requested virtual address. If these identifiers match and the virtual address retained in the DLAT matches the currently requested virtual address, the translation stored in the DLAT may be used. If the identifiers or virtual address don't match, a new translation must be performed using the set of conversion tables associated with the currently requested address.