公开(公告)号：FR2423822A1

公开(公告)日：1979-11-16

申请号：FR7905120

申请日：1979-02-22

Applicant: IBM

Inventor： GANNON PATRICK M ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W

IPC: C08F4/46 ,  G06F9/308 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0886 ,  G06F9/06 ,  G11C9/06

公开(公告)号：FR2413716A1

公开(公告)日：1979-07-27

申请号：FR7836587

申请日：1978-12-20

Applicant: IBM

Inventor： HUGHES JEFFREY F ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W ,  STONE STANLEY E

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/10

Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.

公开(公告)号：CA1103369A

公开(公告)日：1981-06-16

申请号：CA314524

申请日：1978-10-27

Applicant: IBM

Inventor： HUGHES JEFFREY F ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W ,  STONE STANLEY E

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00

Abstract: MULTI-INSTRUCTION STREAM BRANCH PROCESSING MECHANISM In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of pointers identify a particular one of the multiple instruction buffers. A first pointer identifies one of the instruction buffers which is to receive the target instruction identified by a branch instruction decoded from another instruction stream contained in another instruction buffer. Various branch instructions are predicted to be successful or unsuccessful, and in response to this prediction, a second pointer is set to control gating of the proper instruction to an instruction decoding mechanism, either from the original instruction stream of the branch instruction or from the instruction buffer which contains the target instruction. A third pointer identifies the one of the multiple instruction buffers which contained the instruction last transferred to the instruction execution unit. A fourth pointer, contained in a queue of predecoded instructions, and which is associated with each branch instruction to be presented to the instruction execution unit, identifies the one of the instruction buffers which was enabled to receive the target instruction. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will reset various pointers and busy triggers associated with each instruction buffer, set one pointer to the same condition as another pointer, or leave certain pointers in a present state, such that the next sequential instruction to be transferred to the instruction execution unit is from the proper instruction stream based on the result of the branch on condition instruction.

公开(公告)号：FR2413716B1

公开(公告)日：1986-02-21

申请号：FR7836587

申请日：1978-12-20

Applicant: IBM

Inventor： HUGHES JEFFREY F ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W ,  STONE STANLEY E

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/18

Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.