公开(公告)号：JP2002132500A

公开(公告)日：2002-05-10

申请号：JP2001282724

申请日：2001-09-18

Applicant: IBM

Inventor： BRUCE C JAMEY ,  MARK A CHECK ,  LIPTAY JOHN S

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method of detecting an address generating interlock and its system in a pipeline data processor. SOLUTION: A step accumulating a plurality of vectors over predefined numbers of a processor clock cycle and following vectors are responded to following clock cycles in the method. The method is comprised of a step accumulating status of all-purpose registers with one and more in a plurality of vectors having the same bit position concerning to each vector of a plurality of the vectors corresponding to specific all-purpose registers, a step generating a list for renewal of reserved all-purpose registers in logic combination of a plurality of vectors, and a step discriminating existence of the address generating interlock from the list for renewal of reserved all-purpose register.

公开(公告)号：FR2413716B1

公开(公告)日：1986-02-21

申请号：FR7836587

申请日：1978-12-20

Applicant: IBM

Inventor： HUGHES JEFFREY F ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W ,  STONE STANLEY E

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/18

Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.

公开(公告)号：CA1303225C

公开(公告)日：1992-06-09

申请号：CA570361

申请日：1988-06-24

Applicant: IBM

Inventor： LIPTAY JOHN S

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G11C11/419

Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.

公开(公告)号：AU606180B2

公开(公告)日：1991-01-31

申请号：AU1907588

申请日：1988-07-15

Applicant: IBM

Inventor： LIPTAY JOHN S

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G11C11/419 ,  G06F9/30

Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.

公开(公告)号：FR2420168B1

公开(公告)日：1986-09-26

申请号：FR7902412

申请日：1979-01-25

Applicant: IBM

Inventor： LIPTAY JOHN S

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/06

公开(公告)号：CA1103369A

公开(公告)日：1981-06-16

申请号：CA314524

申请日：1978-10-27

Applicant: IBM

Inventor： HUGHES JEFFREY F ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W ,  STONE STANLEY E

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00

Abstract: MULTI-INSTRUCTION STREAM BRANCH PROCESSING MECHANISM In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of pointers identify a particular one of the multiple instruction buffers. A first pointer identifies one of the instruction buffers which is to receive the target instruction identified by a branch instruction decoded from another instruction stream contained in another instruction buffer. Various branch instructions are predicted to be successful or unsuccessful, and in response to this prediction, a second pointer is set to control gating of the proper instruction to an instruction decoding mechanism, either from the original instruction stream of the branch instruction or from the instruction buffer which contains the target instruction. A third pointer identifies the one of the multiple instruction buffers which contained the instruction last transferred to the instruction execution unit. A fourth pointer, contained in a queue of predecoded instructions, and which is associated with each branch instruction to be presented to the instruction execution unit, identifies the one of the instruction buffers which was enabled to receive the target instruction. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will reset various pointers and busy triggers associated with each instruction buffer, set one pointer to the same condition as another pointer, or leave certain pointers in a present state, such that the next sequential instruction to be transferred to the instruction execution unit is from the proper instruction stream based on the result of the branch on condition instruction.

公开(公告)号：CA2058392A1

公开(公告)日：1992-07-17

申请号：CA2058392

申请日：1991-12-23

Applicant: IBM

Inventor： BERSTIS VIKTORS ,  LIPTAY JOHN S ,  PEDERSEN RAYMOND J

IPC: G06F9/34 ,  G06F9/355 ,  G06F9/38

Abstract: P09-90-014 STORAGE OPERAND MANAGEMENT In a computer system having a system memory, m architected logical register and an array of n physical registers, where n is greater than m, a method of managing storage operands including the steps of: detecting the decoding of an instruction having at least one field specifying a storage operand; identifying an available one of the physical registers; fetching the storage operand from the system memory; loading the storage operand into the available one of the physical registers; and executing the instruction, using the storage operand stored in the one of the physical registers.

公开(公告)号：AU1907588A

公开(公告)日：1989-01-27

申请号：AU1907588

申请日：1988-07-15

Applicant: IBM

Inventor： LIPTAY JOHN S

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G11C11/419 ,  G06F9/30

Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.

公开(公告)号：FR2420168A1

公开(公告)日：1979-10-12

申请号：FR7902412

申请日：1979-01-25

Applicant: IBM

Inventor： LIPTAY JOHN S

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/06

公开(公告)号：FR2413716A1

公开(公告)日：1979-07-27

申请号：FR7836587

申请日：1978-12-20

Applicant: IBM

Inventor： HUGHES JEFFREY F ,  LIPTAY JOHN S ,  RYMARCZYK JAMES W ,  STONE STANLEY E

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/10

Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.