公开(公告)号：DE2223699A1

公开(公告)日：1972-12-21

申请号：DE2223699

申请日：1972-05-16

Applicant: IBM

Inventor： EMESE MAGDO INGRID ,  MAGDO STEVEN

IPC: H01L21/20 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L23/535 ,  H01L27/00 ,  H01L19/00

Abstract: 1360130 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [18 June 1971] 24380/72 Heading H1K A method of making a semi-conductor device comprises forming a dielectric layer on a monocrystalline substrate, opening a window in the layer, growing an epitaxial layer in the window and continuing the growth over the dielectric layer surrounding the window thus forming monocrystalline material within and above the window and polycrystalline material above the dielectric, forming a component in the monocrystalline material and applying a contact for the component to the polycrystalline material, the lateral extent of the polycrystalline material being bounded by a second dielectric layer formed on the first layer. In a first embodiment, Figs. 1 to 4, a bi-polar transistor is produced by diffusing P, As or Sb through a mask to form an N + -type subcollector region 24 in a P--type substrate 20, removing the mask and oxidizing to form a thin protective layer on which a first thick SiO 2 layer 23 is applied by sputtering. A thin layer 25 of Si 3 N 4 is deposited and covered with a second thick SiO 2 layer 26. Apertures 28, 30, 32 are selectively etched through the insulating layers and P-type Si is epitaxially deposited in the apertures to the thickness of the first SiO 2 layer 23. These deposits are monocrystalline and in the apertures 30, 32 above the subcollector region the P-type material is converted to N-type due to redistribution of impurities. The part of the top SiO 2 layer surrounding the aperture 32 is removed by selective etching to define the device area 34, the Si 3 N 4 layer 25 preventing removal of the lower SiO 2 layer. P-type Si is then epitaxially deposited to fill the apertures. The material in the device region 34 is monocrystalline above the aperture 32 and is surrounded with polycrystalline material over the exposed Si 3 N 4 layer. The material deposited in the upper part of the aperture 30 is converted to N-type by diffusion to form a collector reach-through and an N + -type emitter region 36 is diffused into the monocrystalline part of the device region which forms the base of the transistor. A layer of metal is deposited and patterned to form contacts, the base connection being made via the polycrystalline material. The device may be modified to produce an inverse transistor so that region 36 forms the collector. In a second embodiment, Figs. 5 to 8 (not shown), a P--type Si wafer (20) with an N + -type sub-collector region (24) is provided with an insulating layer (26) by sputtering a thick layer SiO 2 and covering with a thin layer of Si 3 N 4 . Two apertures (40, 42) are formed above the sub-collector region and one aperture (44) which defines a resistor region is formed above the substrate. Si is epitaxially deposited in the openings and over the top of the insulating layer, the material being undoped or N--type until the apertures are filled and the dopant then being changed to P-type. The deposited material is monocrystalline within and above the apertures (40, 42, 44) but polycrystalline above the insulating layer. The surface is oxidized and unwanted portions of the epitaxial layer are etched away to leave the monocrystalline region surrounded by polycrystalline material over one of the apertures to form the device region and to leave the monocrystalline deposits within the other apertures. The surface is re-oxidized and P or As is selectively diffused into the reach-through and resistor areas, and As, P or Sb is selectively diffused-in to form the N + -type emitter region in the monocrystalline part of the base region and to heavily dope the collector and resistor contact regions. Al electrodes are then applied. In a modification, Fig. 9 (not shown), instead of removing parts of the deposited P-type layer, isolation is achieved by selective thermal oxidation of the polycrystalline Si. In another embodiment, Figs. 10 to 12 (not shown) an N + -type sub-collector region (24) is formed in a P-type substrate (20), the surface is oxidized (62) and covered with Si 3 N 4 (64) and two windows (66, 68) are opened above the sub-collector region. A thick layer (70) of SiO 2 is pyrolytically deposited and windows (72, 74) are opened aligned with those in the underlayers but one being of larger area. An undoped layer (76) is epitaxially grown in the windows, the deposit in the smaller windows being monocrystalline and that in the other window having a monocrystalline cone surrounded by polycrystalline material. P or As is selectively diffused onto the collector reach-through region (80), a P-type impurity is diffused onto the monocrystalline and polycrystalline base region and finally P or As is selectively diffused to form the emitter region (81) in the monocrystalline part of the base region and to form the collector contact region. Contacts are applied as before. In a further embodiment, Figs. 13 to 15 (not shown), an MOS transistor is produced by thermally oxidizing the surface of a P--type layer (82), depositing a layer (86) of Si 3 N 4 , opening a window (88) in the Si 3 N 4 layer, depositing a thick layer (90) of SiO 2 pyrolytically or by sputtering, and opening a larger window (92) in the thick SiO 2 layer. P-type material is epitaxially deposited to fill the windows and forms a monocrystalline core (94) flanked by polycrystalline material. The surface is oxidized and P or As is selectively diffused into the polycrystalline material to form the source and drain regions (98, 100), the edges of the monocrystalline region also being doped to form the active parts of these regions. The device is then completed by conventional processing.

公开(公告)号：CA1019462A

公开(公告)日：1977-10-18

申请号：CA213805

申请日：1974-11-15

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/337 ,  H01L21/762 ,  H01L27/00 ,  H01L29/00 ,  H01L29/73 ,  H01L29/808

Abstract: A space charge limited transistor formed on a high resistivity substrate of at least 10,000 ohm-centimeter silicon of one conductivity type. One surface of the substrate is provided with spaced recessed oxide regions. The alternate spaces between the oxide regions are occupied by impurity zones of said one conductivity type. The intervening alternate spaces between the oxide regions are occupied by impurity zones of the other conductivity type. The impurity concentrations of the aforesaid impurity zones are at least several orders of magnitude higher than that of the substrate where the zones are separated from each other by the aforesaid oxide regions. The dielectric relaxation time is much larger than the carrier transit time within the substrate below and between adjacent impurity zones of the same conductivity type.

公开(公告)号：AU8100475A

公开(公告)日：1976-11-11

申请号：AU8100475

申请日：1975-05-09

Applicant: IBM

Inventor： MAGDO STEVEN

IPC: H01L31/10 ,  H01L27/144 ,  H01L27/146 ,  H01L31/00 ,  H01L15/00

Abstract: 1501962 Photosensitive semi - conductor devices INTERNATIONAL BUSINESS MACHINES CORP 5 May 1975 [24 June 1974] 18673/75 Heading H1K A space-charge-limited phototransistor structure comprises lateral emitter, base and collector regions 8, 6, 5 at the surface of a semi-conductor substrate 2 of resistivity at least 10,000 ohm-cm. beneath which, along line B, a space-charge limited current flows between the emitter and collector when the surface base area receives incident radiant energy. More electron-hole separation occurs in region B than in the base region 6, the depth of the base region being less than the reciprocal of the absorption coefficient of the radiant energy. In the integrated circuit shown, adjacent transistors are isolated by a region of opposite type to that of the substrate reverse biased with respect to the collector regions. The base region is at floating potential and when the base surface is illuminated, the collector, which is reverse biased, collects electrons from the pairs generated in both the P base and lower N regions. The remaining holes tend to forward-bias the emitter-base junctions along lines A and B to initiate phototransistor action. Metal shields (40) (Fig. 4, not shown) may be placed over the isolation region and the effective base area may be increased, whilst maintaining the required base width, by extending the collectorbase junction along certain portions only (Figs. 2, 3, not shown). An array of such phototransistors (Fig. 5, not shown) may be used in a document reading scanner.

公开(公告)号：CA992219A

公开(公告)日：1976-06-29

申请号：CA171590

申请日：1973-05-15

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/73 ,  H01L21/22 ,  H01L21/32 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/082 ,  H01L29/78

Abstract: A method of fabricating a planar dielectrically isolated semiconductor device by depositing a surface layer of dielectric material on a major surface of a monocrystalline substrate, removing portions of the layer to define annular channels, thermally oxidizing the exposed surface areas thereby forming annular ridges of SiO2, removing portions of the dielectric layer, selectively growing an epitaxial silicon layer over the surface wherein the surfaces of the annular ridges of SiO2 and the regions of epitaxial silicon are substantially co-planar.

公开(公告)号：FR2276697A1

公开(公告)日：1976-01-23

申请号：FR7514482

申请日：1975-04-30

Applicant: IBM

Inventor： MAGDO STEVEN

IPC: H01L27/144 ,  H01L31/10 ,  H01L27/146 ,  H01L31/00

Abstract: 1501962 Photosensitive semi - conductor devices INTERNATIONAL BUSINESS MACHINES CORP 5 May 1975 [24 June 1974] 18673/75 Heading H1K A space-charge-limited phototransistor structure comprises lateral emitter, base and collector regions 8, 6, 5 at the surface of a semi-conductor substrate 2 of resistivity at least 10,000 ohm-cm. beneath which, along line B, a space-charge limited current flows between the emitter and collector when the surface base area receives incident radiant energy. More electron-hole separation occurs in region B than in the base region 6, the depth of the base region being less than the reciprocal of the absorption coefficient of the radiant energy. In the integrated circuit shown, adjacent transistors are isolated by a region of opposite type to that of the substrate reverse biased with respect to the collector regions. The base region is at floating potential and when the base surface is illuminated, the collector, which is reverse biased, collects electrons from the pairs generated in both the P base and lower N regions. The remaining holes tend to forward-bias the emitter-base junctions along lines A and B to initiate phototransistor action. Metal shields (40) (Fig. 4, not shown) may be placed over the isolation region and the effective base area may be increased, whilst maintaining the required base width, by extending the collectorbase junction along certain portions only (Figs. 2, 3, not shown). An array of such phototransistors (Fig. 5, not shown) may be used in a document reading scanner.

公开(公告)号：CA976666A

公开(公告)日：1975-10-21

申请号：CA144164

申请日：1972-06-08

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L21/20 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L23/535 ,  H01L27/00

Abstract: 1360130 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [18 June 1971] 24380/72 Heading H1K A method of making a semi-conductor device comprises forming a dielectric layer on a monocrystalline substrate, opening a window in the layer, growing an epitaxial layer in the window and continuing the growth over the dielectric layer surrounding the window thus forming monocrystalline material within and above the window and polycrystalline material above the dielectric, forming a component in the monocrystalline material and applying a contact for the component to the polycrystalline material, the lateral extent of the polycrystalline material being bounded by a second dielectric layer formed on the first layer. In a first embodiment, Figs. 1 to 4, a bi-polar transistor is produced by diffusing P, As or Sb through a mask to form an N + -type subcollector region 24 in a P--type substrate 20, removing the mask and oxidizing to form a thin protective layer on which a first thick SiO 2 layer 23 is applied by sputtering. A thin layer 25 of Si 3 N 4 is deposited and covered with a second thick SiO 2 layer 26. Apertures 28, 30, 32 are selectively etched through the insulating layers and P-type Si is epitaxially deposited in the apertures to the thickness of the first SiO 2 layer 23. These deposits are monocrystalline and in the apertures 30, 32 above the subcollector region the P-type material is converted to N-type due to redistribution of impurities. The part of the top SiO 2 layer surrounding the aperture 32 is removed by selective etching to define the device area 34, the Si 3 N 4 layer 25 preventing removal of the lower SiO 2 layer. P-type Si is then epitaxially deposited to fill the apertures. The material in the device region 34 is monocrystalline above the aperture 32 and is surrounded with polycrystalline material over the exposed Si 3 N 4 layer. The material deposited in the upper part of the aperture 30 is converted to N-type by diffusion to form a collector reach-through and an N + -type emitter region 36 is diffused into the monocrystalline part of the device region which forms the base of the transistor. A layer of metal is deposited and patterned to form contacts, the base connection being made via the polycrystalline material. The device may be modified to produce an inverse transistor so that region 36 forms the collector. In a second embodiment, Figs. 5 to 8 (not shown), a P--type Si wafer (20) with an N + -type sub-collector region (24) is provided with an insulating layer (26) by sputtering a thick layer SiO 2 and covering with a thin layer of Si 3 N 4 . Two apertures (40, 42) are formed above the sub-collector region and one aperture (44) which defines a resistor region is formed above the substrate. Si is epitaxially deposited in the openings and over the top of the insulating layer, the material being undoped or N--type until the apertures are filled and the dopant then being changed to P-type. The deposited material is monocrystalline within and above the apertures (40, 42, 44) but polycrystalline above the insulating layer. The surface is oxidized and unwanted portions of the epitaxial layer are etched away to leave the monocrystalline region surrounded by polycrystalline material over one of the apertures to form the device region and to leave the monocrystalline deposits within the other apertures. The surface is re-oxidized and P or As is selectively diffused into the reach-through and resistor areas, and As, P or Sb is selectively diffused-in to form the N + -type emitter region in the monocrystalline part of the base region and to heavily dope the collector and resistor contact regions. Al electrodes are then applied. In a modification, Fig. 9 (not shown), instead of removing parts of the deposited P-type layer, isolation is achieved by selective thermal oxidation of the polycrystalline Si. In another embodiment, Figs. 10 to 12 (not shown) an N + -type sub-collector region (24) is formed in a P-type substrate (20), the surface is oxidized (62) and covered with Si 3 N 4 (64) and two windows (66, 68) are opened above the sub-collector region. A thick layer (70) of SiO 2 is pyrolytically deposited and windows (72, 74) are opened aligned with those in the underlayers but one being of larger area. An undoped layer (76) is epitaxially grown in the windows, the deposit in the smaller windows being monocrystalline and that in the other window having a monocrystalline cone surrounded by polycrystalline material. P or As is selectively diffused onto the collector reach-through region (80), a P-type impurity is diffused onto the monocrystalline and polycrystalline base region and finally P or As is selectively diffused to form the emitter region (81) in the monocrystalline part of the base region and to form the collector contact region. Contacts are applied as before. In a further embodiment, Figs. 13 to 15 (not shown), an MOS transistor is produced by thermally oxidizing the surface of a P--type layer (82), depositing a layer (86) of Si 3 N 4 , opening a window (88) in the Si 3 N 4 layer, depositing a thick layer (90) of SiO 2 pyrolytically or by sputtering, and opening a larger window (92) in the thick SiO 2 layer. P-type material is epitaxially deposited to fill the windows and forms a monocrystalline core (94) flanked by polycrystalline material. The surface is oxidized and P or As is selectively diffused into the polycrystalline material to form the source and drain regions (98, 100), the edges of the monocrystalline region also being doped to form the active parts of these regions. The device is then completed by conventional processing.

公开(公告)号：DE2458735A1

公开(公告)日：1975-07-10

申请号：DE2458735

申请日：1974-12-12

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/337 ,  H01L21/762 ,  H01L27/00 ,  H01L29/00 ,  H01L29/73 ,  H01L29/808 ,  H01L29/10

Abstract: A space charge limited transistor formed on a high resistivity substrate of at least 10,000 ohm-centimeter silicon of one conductivity type. One surface of the substrate is provided with spaced recessed oxide regions. The alternate spaces between the oxide regions are occupied by impurity zones of said one conductivity type. The intervening alternate spaces between the oxide regions are occupied by impurity zones of the other conductivity type. The impurity concentrations of the aforesaid impurity zones are at least several orders of magnitude higher than that of the substrate where the zones are separated from each other by the aforesaid oxide regions. The dielectric relaxation time is much larger than the carrier transit time within the substrate below and between adjacent impurity zones of the same conductivity type.

公开(公告)号：DE2407189A1

公开(公告)日：1974-10-24

申请号：DE2407189

申请日：1974-02-15

Applicant: IBM

Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN

IPC: H01L27/06 ,  H01L21/00 ,  H01L21/285 ,  H01L21/60 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/08 ,  H01L29/00 ,  H01L29/47 ,  H01L29/872 ,  H01L19/00

Abstract: A planar integrated circuit structure having a dielectrically isolated Schottky Barrier contact.

公开(公告)号：DE2860999D1

公开(公告)日：1981-11-26

申请号：DE2860999

申请日：1978-07-03

Applicant: IBM

Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN

IPC: H01L21/302 ,  G03F1/20 ,  H01L21/027 ,  H01L21/033 ,  H01L21/266 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/00 ,  H01L29/06

公开(公告)号：CA1048656A

公开(公告)日：1979-02-13

申请号：CA255057

申请日：1976-06-16

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/78 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/73 ,  H01L27/02 ,  H01L29/72 ,  H01L21/70

Abstract: FABRICATING HIGH PERFORMANCE INTEGRATED BIPOLAR AND COMPLEMENTARY FIELD EFFECT TRANSISTORS A method for making dielectrically isolated bipolar and field effect transistors in the same substrate and a semiconductor integrated circuit so-made. The method consists of forming a first region of one conductivity type in a monocrystalline semiconductor substrate on a first type, forming second and third regions having different diffusion rates in the substrate, forming a monocrystalline layer of the other conductivity type, adding impurity to the second region, depositing a dielectric layer over the monocrystalline layer, forming openings in the dielectric layer over the first and third regions and another location in the monocrystalline layer, and depositing a layer of silicon over the dielectric layer and the openings. The impurities in the third region are outdiffused into the monocrystalline region over it to form the channel region of a Field Effect transistor. The regions of the layer of silicon are dielectrically isolated from one another and emitter and base regions of a bipolar transistor are selectively formed in the monocrystalline region over subcollector regions. Source and drain regions for a field effect transistor are formed over the third region and the another location to form both channel types of field effect transistors.