公开(公告)号：CA1191971A

公开(公告)日：1985-08-13

申请号：CA408724

申请日：1982-08-04

Applicant: IBM

Inventor： GOTH GEORGE R ,  MALAVIYA SHASHI D

IPC: H01L27/00 ,  H01L21/72

Abstract: Lateral Device Structures Using Self-Aligned Fabrication Techniques Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithograph. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

公开(公告)号：CA1166760A

公开(公告)日：1984-05-01

申请号：CA378808

申请日：1981-06-02

Applicant: IBM

Inventor： GOTH GEORGE R ,  MAGDO INGRID E ,  MALAVIYA SHASHI D

IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/70 ,  H05K3/02 ,  H01L27/02

Abstract: SELF-ALIGNED METAL PROCESS FOR INTEGRATED CIRCUIT METALLIZATION A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive FI9-80-010 ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. FI9-80-010

公开(公告)号：CA1118851A

公开(公告)日：1982-02-23

申请号：CA313490

申请日：1978-10-16

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03L7/16 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H04L7/033 ,  H03L7/00

Abstract: VARIABLE FREQUENCY OSCILLATOR WITH STABLE CENTER FREQUENCY Disclosed is a variable frequency oscillator system having a very stable center frequency and adjustable over a wide range of frequency excursions. A pair of variable frequency oscillators (VFO) are fabricated on the same integrated circuit chip so that corresponding components have substantially identical characteristics. The first VFO and a highly stable crystal oscillator provide comparable frequency output signals to a phase locked loop which provides as its output a correction signal (voltage or current) to lock the first VFO to the crystal oscillator frequency. The frequency of the second VFO in turn will be essentially the same as that of the first because of similarities in components and operating conditions as well as sharing of the correction signal between the two VFO's. The output of the second VFO provides the local clock signal and can be varied further by a second correction signal. In one embodiment, the second correction signal is provided by a second phase locked loop.

公开(公告)号：CA1052892A

公开(公告)日：1979-04-17

申请号：CA239236

申请日：1975-11-04

Applicant: IBM

Inventor： MALAVIYA SHASHI D ,  VORA MADHUKAR B ,  WILSON WILLIAM T

IPC: H01L27/146 ,  H01L31/112 ,  H01L31/10 ,  H01L27/14 ,  H01L29/80

Abstract: RANDOM ACCESS SOLID-STATE IMAGE SENSOR WITH NON-DESTRUCTIVE READ-OUT A solid state analog image sensor is disclosed in which the video input to the sensor is stored as a charge on a floating gate in a cell. The cell itself consists of a single J-FET with Schottky barrier contact to the metal word line. All associated address and drive/sense circuits are located around the active cell area. By filling up the active area with only the J-FET's and relegating the rest of the circuitry to the peripheral, inactive region, high picture resolution is obtained.

公开(公告)号：CA1238117A

公开(公告)日：1988-06-14

申请号：CA502055

申请日：1986-02-18

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H01L29/808 ,  H01L21/033 ,  H01L21/308 ,  H01L21/331 ,  H01L21/337 ,  H01L21/764 ,  H01L21/822 ,  H01L27/04 ,  H01L29/06 ,  H01L29/47 ,  H01L29/73 ,  H01L29/78 ,  H01L29/80 ,  H01L29/86 ,  H01L29/872 ,  H01L21/72

Abstract: Disclosed is a process of fabricating a submicron wide single crystal silicon structure protruding from a monolithic silicon body. Starting with a single crystal N silicon body having a P region, an insulator stud of sub micron width and length dictated by the limits of lithography is formed on the P region. Using the stud as a mask, the P region is etched forming the top narrow portion having the stud width projecting from the silicon body. On the exposed sides of the top portion oxide walls are formed and the etching continued forming the middle portion of a width exceeding that of the top portion. An oxide-nitride wall is established on the exposed sides of the middle portion and, using the resulting structure as a mask, the etching is continued to completely etch through the P region and a substantial portion of the underlying N silicon body thereby forming a free-standing silicon protrusion structure. Thick oxide walls are formed on the just exposed sides of the silicon.

公开(公告)号：CA1058753A

公开(公告)日：1979-07-17

申请号：CA237272

申请日：1975-10-08

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: G11C11/40 ,  H01L29/70

Abstract: D. C. STABLE SINGLE DEVICE MEMORY CELL A single device, D. C. stable memory cell comprising a bistable bipolar transistor having a lightly-doped base and an emitter which is substantially coextensive with the base.

公开(公告)号：CA1015039A

公开(公告)日：1977-08-02

申请号：CA211518

申请日：1974-10-16

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03D3/02 ,  H03D13/00

Abstract: A phase discriminator, for operation in a phase-locked loop, which is characterized by a virtually infinite capture range. The discriminator comprises circuit means responsive to the input data and clock pulses for generating a signal having a duration indicative of the phase difference between the pulses, a flip-flop which identifies the phase relationship between the pulses, and a current switch circuit responsive to the flip-flop output for generating an output pulse having a potential level indicative of the phase relationship between the input pulses, and responsive to the circuit means for generating the output pulse for a duration proportional to the phase difference between them. The circuit is also capable of locking pulses of widely different frequencies and tolerates a large variation of input pulse widths.

公开(公告)号：FR2296267A1

公开(公告)日：1976-07-23

申请号：FR7534721

申请日：1975-11-05

Applicant: IBM

Inventor： MALAVIYA SHASHI D ,  VORA MADHUKAR B ,  WILSON WILLIAM T

IPC: H01L27/146 ,  H01L31/112 ,  H01L27/14 ,  H01J29/45

Abstract: A solid state analog image sensor is disclosed in which the video input to the sensor is stored as a charge on a floating gate in a cell. The cell itself consists of a single J-FET with Schottky barrier contact to the metal word line. All associated address and drive/sense circuits are located around the active cell area. By filling up the active area with only the J-FET's and relegating the rest of the circuitry to the peripheral, inactive region, high picture resolution is obtained.

公开(公告)号：CA982663A

公开(公告)日：1976-01-27

申请号：CA184805

申请日：1973-11-01

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03K3/289

Abstract: A binary divider circuit of the master-slave type. The master bistable flip-flop and the slave bistable flip-flop are arranged in series between the voltage supply lines so that current flows from one of the supply lines through one of the bistable circuits and then through the other of the bistable circuits into the other supply line. The series arrangement of the bistable circuits provides reduced power dissipation and increased switching speed. The disclosed embodiment further comprises diodes extending from one voltage supply line to the master bistable circuit for bypassing current around the slave bistable circuit and to the master bistable circuit so as to provide higher output power and/or faster switching speed for the master bistable circuit. The diodes further function as a voltage regulator for maintaining the voltage across each bistable circuit approximately constant to prevent the bistable circuits from interacting with each other as their respective impedances vary during switching operations.