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公开(公告)号：JP2003016779A
公开(公告)日：2003-01-17
申请号：JP2001199723
申请日：2001-06-29
Inventor： SUNANAGA TOSHIO , MIYATAKE HISATADA , KITAMURA TSUNEJI , UMEZAKI HIROSHI , NODA HIROYOSHI , ASANO HIDEO
IPC: G11C11/14 , G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
Abstract: PROBLEM TO BE SOLVED: To provide a storage circuit block in which a write-in current can be reduced, and to provide a method for accessing the storage circuit block.
SOLUTION: This storage circuit block 10 comprises a means for holding data stored in a sense amplifier 24, a means holding data inputted to an input/ output pad 22, and a means for comparing data held in the means holding data stored in the sense amplifier 24 with data held in the means holding data inputted to the input/output pad 22.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供可以减少写入电流的存储电路块，并提供访问存储电路块的方法。 解决方案：该存储电路块10包括用于保存存储在读出放大器24中的数据的装置，保持输入到输入/输出焊盘22的数据的装置，以及用于比较保存在存储在读出放大器 24，其中保存有保持输入到输入/输出垫22的数据的装置中的数据。
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公开(公告)号：JP2003016778A
公开(公告)日：2003-01-17
申请号：JP2001199620
申请日：2001-06-29
Inventor： SUNANAGA TOSHIO , MIYATAKE HISATADA , KITAMURA TSUNEJI , UMEZAKI HIROSHI , NODA HIROYOSHI , ASANO HIDEO
CPC classification number: G11C11/15 , G11C2207/2263
Abstract: PROBLEM TO BE SOLVED: To provide a storage circuit block in which a write-in current can be reduced, and to provide a method for accessing the storage circuit block. SOLUTION: This device comprises a means for detecting a data write-in current flowing in a bit line 32, and a means for generating a stop signal of a data write-in current flowing in the bit line 32 and a write-in word line 30.
Abstract translation: 要解决的问题：提供可以减少写入电流的存储电路块，并提供访问存储电路块的方法。 解决方案：该装置包括用于检测在位线32中流动的数据写入电流的装置，以及用于产生在位线32中流动的数据写入电流的停止信号的装置和写入字线 30。
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13.发明专利Memory cell, storage circuit block, data write method and data read method 审中-公开存储单元，存储电路块，数据写入方法和数据读取方法
公开(公告)号：JP2002368196A
公开(公告)日：2002-12-20
申请号：JP2001161718
申请日：2001-05-30
Inventor： MIYATAKE HISATADA , SUNANAGA TOSHIO , KITAMURA TSUNEJI
IPC: G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC classification number: H01L27/228 , B82Y10/00 , G11C11/16
Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, a storage circuit block, a data write method and data read method in which production yield is high, cost is low, reliability is high, and the chip area can be reduced by reducing the number of metal wiring layers. SOLUTION: A memory cell 12 is configured so as to include metal lines 16 intersecting with bit liens 14 in a no-contact manner therewith, and a second wiring structure 24 for connecting the lines 16 to switching elements 20. A write circuit 26 for making a current flow through the lines 16 and a ground 28 are connected to the lines 16 via a switch 30 for selecting the circuit 26 and the ground 28.
Abstract translation: 要解决的问题：为了提供一种存储单元，存储电路块，数据写入方法和数据读取方法，其中生产率高，成本低，可靠性高，并且可以通过减少数量来减少芯片面积 的金属布线层。 解决方案：存储单元12被配置为包括与位留置体14以不接触的方式相交的金属线16，以及用于将线16连接到开关元件20的第二布线结构24.用于制造的写入电路26 通过线16和地线28的电流通过用于选择电路26和地面28的开关30连接到线路16。
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公开(公告)号：JP2000137989A
公开(公告)日：2000-05-16
申请号：JP30813198
申请日：1998-10-29
Applicant: IBM
Inventor： MIYATAKE HISATADA , TANAKA MASAHIRO , MORI YOTARO
Abstract: PROBLEM TO BE SOLVED: To provide a high speed and low power consumption single signal detection circuit (sense amplifier circuit). SOLUTION: In the sense amplifier circuit for detecting/amplifying a signal on a signal line, an inverter pair 11, 12 connecting an output of an inverter to an input of the other side inverter each other and sensing switches being first, second switches 13, 14 connected to source ends of respective inverters of the inverter pair and a constant current source 15, and that the signal line 10 is connected to the first switch, and reference potential Vref is connected to the second switch are incorporated, and the drive force of the first switch is made larger than the same of the second switch.
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公开(公告)号：DE602004022157D1
公开(公告)日：2009-09-03
申请号：DE602004022157
申请日：2004-04-13
Applicant: IBM
Inventor： SUNAGA TOSHIO , HOSOKAWA KOHJI , MIYATAKE HISATADA
IPC: G11C11/406
Abstract: To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by detailedly setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.
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Patent Agency Ranking
公开(公告)号：AT437439T
公开(公告)日：2009-08-15
申请号：AT04727148
申请日：2004-04-13
Applicant: IBM
Inventor： SUNAGA TOSHIO , HOSOKAWA KOHJI , MIYATAKE HISATADA
IPC: G11C11/406
Abstract: To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by detailedly setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.
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公开(公告)号：JP2013118449A
公开(公告)日：2013-06-13
申请号：JP2011264098
申请日：2011-12-01
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation Inventor： YAMADA GEN , ISHII MASATOSHI , MIYATAKE HISATADA
IPC: H03K5/06 , H03K5/1532
Abstract: PROBLEM TO BE SOLVED: To provide a pulse width stretching circuit and method which stretch a pulse width of a pulse signal without causing a glitch in a small circuit scale.SOLUTION: A pulse width stretching circuit 500 includes: a pulse delay circuit 110 that receives an input pulse signal a to output a delayed pulse signal b; and a pulse adjustment circuit 510 that is connected to the pulse delay circuit 110, and receives the input pulse signal a and the delayed pulse signal b to output an output pulse signal c having a longer pulse width than that of the input pulse signal a. The pulse adjustment circuit 510 generates a leading edge of the output pulse signal c in response to a leading edge of the input pulse signal a, keeps a state of displacement caused by the leading edge of the output pulse signal c for a period of time longer than a total time of pulse duration of both input pulse signal a and delayed pulse signal b, and generates a trailing edge of the output pulse signal c in response to a trailing edge of the delayed pulse signal b.
Abstract translation: 要解决的问题：提供一种延长脉冲信号的脉冲宽度而不会在小电路规模中产生毛刺的脉宽拉伸电路和方法。 解决方案：脉宽延伸电路500包括：脉冲延迟电路110，其接收输入脉冲信号a以输出延迟的脉冲信号b; 以及连接到脉冲延迟电路110的脉冲调整电路510，并且接收输入脉冲信号a和延迟脉冲信号b，以输出具有比输入脉冲信号a的脉冲宽度更大的脉冲宽度的输出脉冲信号c。 脉冲调整电路510响应于输入脉冲信号a的前沿产生输出脉冲信号c的前沿，将输出脉冲信号c的前沿引起的位移状态保持一段时间 比输入脉冲信号a和延迟脉冲信号b的脉冲持续时间的总时间长，并且响应于延迟脉冲信号b的后沿而产生输出脉冲信号c的后沿。 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2007095146A
公开(公告)日：2007-04-12
申请号：JP2005281687
申请日：2005-09-28
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： SUNANAGA TOSHIO , MIYATAKE HISATADA
IPC: G11C11/407 , G11C11/403
CPC classification number: G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/4076
Abstract: PROBLEM TO BE SOLVED: To increase a data rate in the data I/O of continuous burst data in a memory. SOLUTION: A memory array, and an access control circuit for controlling access to the memory array are provided. The access control circuit includes an access command circuit (ADRCTL) for receiving first (CE) and second (ADV) input signals to output an access command signal (ACMDS) for notifying memory access, and a command identification circuit (CMDDEC) for receiving the first (CE) and second (ADV) input signals, third (OE) and fourth (WE) input signals, and a clock signal (CLK) to output a command identification signal (WRITE) for specifying the type of an access command signal. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：增加存储器中连续脉冲串数据的数据I / O中的数据速率。 提供了一种用于控制对存储器阵列的访问的存储器阵列和访问控制电路。 访问控制电路包括用于接收第一（CE）和第二（ADV）输入信号以访问用于通知存储器访问的访问命令信号（ACMDS）的访问命令电路（ADRCTL），以及用于接收 第一（CE）和第二（ADV）输入信号，第三（OE）和第四（WE）输入信号，以及时钟信号（CLK），输出用于指定访问命令信号的类型的命令识别信号（WRITE）。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2004030825A
公开(公告)日：2004-01-29
申请号：JP2002187873
申请日：2002-06-27
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： SUNANAGA TOSHIO , MIYATAKE HISATADA , HOSOKAWA KOJI
IPC: G11C11/403 , G11C11/406
Abstract: PROBLEM TO BE SOLVED: To provide a DRAM which performs burst refresh so as to attain low current fresh not limited by a peak current by minimizing operations of a peripheral circuit of a memory array to the utmost, and also to provide its refresh method . SOLUTION: The DRAM is configured to include: a plurality of Z-Lines 24 each corresponding to each of a plurality of word lines 26; and a circuit 10 for looping a selection signal of the Z-Lines 24. The circuit 10 automatically increments or decrements a row address. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP2003016773A
公开(公告)日：2003-01-17
申请号：JP2001199556
申请日：2001-06-29
Inventor： SUNANAGA TOSHIO , MIYATAKE HISATADA , KITAMURA TSUNEJI , ASANO HIDEO , NODA HIROYOSHI , UMEZAKI HIROSHI
IPC: G11C11/14 , G11C11/15 , H01F10/08 , H01L21/8246 , H01L27/105 , H01L43/08
CPC classification number: G11C11/15 , G11C14/0081
Abstract: PROBLEM TO BE SOLVED: To provide a register provided with a non-volatile data storing function. SOLUTION: This device comprises a data write-in block 12 comprising a non-volatile storage element, and a data restoring block 14 for reading out data stored in the non-volatile storage element. MTJ elements 16a, 16b are used as a non-volatile storage element.
Abstract translation: 要解决的问题：提供具有非易失性数据存储功能的寄存器。 解决方案：该装置包括包括非易失性存储元件的数据写入块12和用于读出存储在非易失性存储元件中的数据的数据恢复块14。 MTJ元件16a，16b用作非易失性存储元件。
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