公开(公告)号：JP2002042489A

公开(公告)日：2002-02-08

申请号：JP2000211898

申请日：2000-07-12

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  MORI YOTARO ,  TANAKA MASAHIRO

IPC: G01R31/28 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/56

Abstract: PROBLEM TO BE SOLVED: To eliminate a redundant test step in a test of retrieving operation of an associative memory having a priority encoder. SOLUTION: First, data being different from test data are written as background data (step 21). The background data are read out (step 22), and read-out data are tested (step 23). An address having the lowest priority is specified (step 26), and test data are written (step 27). Retrieving operation is performed (step 28), and it is discriminated whether the test address coincides with the retrieving address. Then, an address having low priority is specified (step 26), and the operation described above is repeated for all addresses (step 32).

公开(公告)号：JP2000222884A

公开(公告)日：2000-08-11

申请号：JP2360299

申请日：1999-02-01

Applicant: IBM

Inventor： TANAKA MASAHIRO

IPC: G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To recognize the existence of an idle word and to recognize a word address without installing an additional circuit at the outside of a memory by a method wherein the output of a valid cell is supplied to an address encoder according to an idle-word detection signal. SOLUTION: An idle-word detection circuit 19 is installed at the front of the input of an address encoder 18. While an idle-word detection signal IWD is used as a control signal, the output (the idle-word retrieval output) of a valid cell 16 as the output of a valid cell 15 and the output (the data retrieval output) of a word matching circuit 17 are changed over so as to be output to the address encoder 18. An idle-word detection signal IWD can be generated as a new signal. When the address of an idle word is always output in an operation other than a data retrieval operation, a data retrieval signal can be used as the idle-word detection signal IWD. According to the idle-word detection signal, the existence of the idle word and its address can be known.

公开(公告)号：JP2000090683A

公开(公告)日：2000-03-31

申请号：JP25854198

申请日：1998-09-11

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/419 ,  G11C16/06 ,  H03K3/356

Abstract: PROBLEM TO BE SOLVED: To provide a sense amplifier circuit in which a micro potential difference can be detected and amplified at high speed with low power consumption and the results can be retained. SOLUTION: Inverter pairs (TP0, TN0, TP1, TN1) are constituted by interconnecting the output of one inverter and the input of the other inverter. Drain of sense transistors (TN2, TN3) is connected in series with the source terminal of each inverter and differential input signal lines 12, 14 are connected with the gate of both sense transistors (TN2, TN3). Source of the sense transistors (TN2, TN3) is connected, as common node, with a transistor TN 4 functioning as a constant current source and an operating switch thus constituting a sense amplifier circuit 10.

公开(公告)号：JP2000137989A

公开(公告)日：2000-05-16

申请号：JP30813198

申请日：1998-10-29

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C7/06 ,  G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To provide a high speed and low power consumption single signal detection circuit (sense amplifier circuit). SOLUTION: In the sense amplifier circuit for detecting/amplifying a signal on a signal line, an inverter pair 11, 12 connecting an output of an inverter to an input of the other side inverter each other and sensing switches being first, second switches 13, 14 connected to source ends of respective inverters of the inverter pair and a constant current source 15, and that the signal line 10 is connected to the first switch, and reference potential Vref is connected to the second switch are incorporated, and the drive force of the first switch is made larger than the same of the second switch.

公开(公告)号：JP2000149573A

公开(公告)日：2000-05-30

申请号：JP31300098

申请日：1998-11-04

Applicant: IBM

Inventor： TANAKA MASAHIRO ,  MORI YOTARO ,  MIYATAKE HISATADA

IPC: G11C15/04 ,  G11C15/00

Abstract: PROBLEM TO BE SOLVED: To enable reduction of power consumption during the search operation by providing an identifying means to identify existence of data stored in a memory block and then retrieval only the memory block which as identified existence of data. SOLUTION: An associative memory is provided with a valid cell 10 for holding data writing of each address within the address range corresponding to a memory block n. When an address ni is designated with an addressing signal, a memory cell M(ni) corresponding to address ni is designated with an address decoder 14 and data is written to the M(ni). When the data is written to M(ni), condition of data V(ni) held by the valid cell corresponding to such address changes and V(ni) is switched to '1' from '0'. When data is written at least to one of the memories from M(n1) to M(ni), it can be determined and detected that data exists in the memory block n.

公开(公告)号：JP2000132978A

公开(公告)日：2000-05-12

申请号：JP30812198

申请日：1998-10-29

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C7/00 ,  G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To speed up a memory and reduce a consumption power by setting a first and a second switches which are turned on and off between an invertor output and a bit line in accordance with a signal on a word line and, a third and a fourth switches which are turned on and off between the bit line and a bit match node in accordance with an invertor output signal. SOLUTION: A voltage amplitude of a word match line 20 is restricted in a range between a higher potential by a threshold voltage of a PMOS transistor with a back gate bias from a ground potential and a lower potential by a threshold of an NMOS transistor NC: 41 with a back gate bias from a power source potential. The range can be made smaller. Accordingly, the voltage amplitude of the word match line 20 becomes small and a consumption power is reduced. When a precharge potential of the word match line 20 is lowered, boosting a bit line is eliminated although the NMOS transistor is used and a high-speed performance is ensured.

公开(公告)号：JPH1166839A

公开(公告)日：1999-03-09

申请号：JP21275897

申请日：1997-08-07

Applicant: IBM

Inventor： TANAKA MASAHIRO ,  MIYATAKE HISATADA ,  MORI YOTARO ,  YAMAZAKI NORITOSHI

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41

Abstract: PROBLEM TO BE SOLVED: To improve a data transfer rate by transferring data plural times in one memory cycle. SOLUTION: A bit line of a memory array l is grouped based on a remainder when the row addresses are divided by the number of groups, and a row address decoding part 4 composing a bit line selection means 3 generates row addresses of the number corresponding to the number of groups according to the row address signal and an access order signal showing the order of the access to the group, and those bit lines are selected by a bit switch 5. Plural latch parts 6a, 6b, 6c each is provided for each group, and the bit line selection means 3 generates plural row addresses consecutive in the same direction referring to the row address signal corresponding to the access order signal.

公开(公告)号：JP2003259625A

公开(公告)日：2003-09-12

申请号：JP2002056152

申请日：2002-03-01

Applicant: IBM

Inventor： TANAKA MASAHIRO ,  RUSSELL JAMES HORTON

IPC: H02M3/07

Abstract: PROBLEM TO BE SOLVED: To provide a charge pump circuit which improves the power factor of an output voltage in approximation to double a supply voltage. SOLUTION: The charge pump circuit 10 is provided with seventh and eighth transistors T7 and T8 between a supply terminal and first and second transistors T1 and T2. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000228090A

公开(公告)日：2000-08-15

申请号：JP2831599

申请日：1999-02-05

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C8/08 ,  G11C7/12 ,  G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To reduce average power consumption in search operation of CAM without affecting performance of CAM. SOLUTION: Relating to each word accompanying bits (valid bit) indicating whether data of at the word is valid or not in CAM, a circuit is constituted so that when a valid bit indicates that the word is invalid, pre-charge is controlled so that pre-charge of a match line of the word is prohibited, and a match line is forcedly in a 'uncoincidence state'. Thereby, power consumption caused by search operation by a data word being not a search object is prevented, and power consumption of search operation of the whole CAM is reduced.