公开(公告)号：JP2004110979A

公开(公告)日：2004-04-08

申请号：JP2002274432

申请日：2002-09-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOSOKAWA KOJI ,  MORI YOTARO

IPC: H01L21/8242 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  H01L27/108

CPC classification number: G11C11/4097 ,  G11C7/18

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM of an MTBL system in which interference noise between bit lines is reduced and density is high.
SOLUTION: Duplication of a sense amplifier (SA) and a bit switch (BSW) in a conventional MTBL system is eliminated, one line of a sense amplifier and a bit switch (BSW/SA) is arranged between each cell area. That is, an array is shifted in the transverse direction and piled vertically, and area is reduced. A pair of bit lines connected every other one in sense amplifiers (SA) arranged in transverse one line is replaced alternately up and down. In a pair of bit lines 11, intersection is performed at one place and interval of bit lines is made wider from the intersection point. Also, in a pair of bit lines 16, intersection is not caused, interval of bit lines is made wider at a half way. In a new MTBL system, in both cases of bit lines connected to the same sense amplifier and bit lines connected to different sense amplifiers out of adjacent bit lines, interval of the bit lines is varied (wider or narrower) at before or after the intersection point. Therefore, interference noise between adjacent any bit lines is reduced.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供其中位线之间的干扰噪声降低并且密度高的MTBL系统的DRAM。 解决方案：消除了常规MTBL系统中的读出放大器（SA）和位开关（BSW）的复制，读取放大器和位开关（BSW / SA）的一行布置在每个单元区域之间。 也就是说，阵列在横向上移动并垂直堆叠，并且面积减小。 在横向一行排列的读出放大器（SA）中每隔一个地连接的一对位线被交替上下替换。 在一对位线11中，在一个位置进行交叉，并且从交点开始位线的间隔更宽。 此外，在一对位线16中，没有引起交叉，位线的间隔在一半处变宽。 在新的MTBL系统中，在连接到相同读出放大器的位线和连接到相邻位线之间的不同读出放大器的位线的两种情况下，位线之​​间的间隔在交点之前或之后变化（更宽或更窄） 点。 因此，相邻任何位线之间的干扰噪声减小。 版权所有（C）2004，JPO

公开(公告)号：JP2002042489A

公开(公告)日：2002-02-08

申请号：JP2000211898

申请日：2000-07-12

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  MORI YOTARO ,  TANAKA MASAHIRO

IPC: G01R31/28 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/56

Abstract: PROBLEM TO BE SOLVED: To eliminate a redundant test step in a test of retrieving operation of an associative memory having a priority encoder. SOLUTION: First, data being different from test data are written as background data (step 21). The background data are read out (step 22), and read-out data are tested (step 23). An address having the lowest priority is specified (step 26), and test data are written (step 27). Retrieving operation is performed (step 28), and it is discriminated whether the test address coincides with the retrieving address. Then, an address having low priority is specified (step 26), and the operation described above is repeated for all addresses (step 32).

公开(公告)号：JP2000090683A

公开(公告)日：2000-03-31

申请号：JP25854198

申请日：1998-09-11

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/419 ,  G11C16/06 ,  H03K3/356

Abstract: PROBLEM TO BE SOLVED: To provide a sense amplifier circuit in which a micro potential difference can be detected and amplified at high speed with low power consumption and the results can be retained. SOLUTION: Inverter pairs (TP0, TN0, TP1, TN1) are constituted by interconnecting the output of one inverter and the input of the other inverter. Drain of sense transistors (TN2, TN3) is connected in series with the source terminal of each inverter and differential input signal lines 12, 14 are connected with the gate of both sense transistors (TN2, TN3). Source of the sense transistors (TN2, TN3) is connected, as common node, with a transistor TN 4 functioning as a constant current source and an operating switch thus constituting a sense amplifier circuit 10.

公开(公告)号：JP2000149573A

公开(公告)日：2000-05-30

申请号：JP31300098

申请日：1998-11-04

Applicant: IBM

Inventor： TANAKA MASAHIRO ,  MORI YOTARO ,  MIYATAKE HISATADA

IPC: G11C15/04 ,  G11C15/00

Abstract: PROBLEM TO BE SOLVED: To enable reduction of power consumption during the search operation by providing an identifying means to identify existence of data stored in a memory block and then retrieval only the memory block which as identified existence of data. SOLUTION: An associative memory is provided with a valid cell 10 for holding data writing of each address within the address range corresponding to a memory block n. When an address ni is designated with an addressing signal, a memory cell M(ni) corresponding to address ni is designated with an address decoder 14 and data is written to the M(ni). When the data is written to M(ni), condition of data V(ni) held by the valid cell corresponding to such address changes and V(ni) is switched to '1' from '0'. When data is written at least to one of the memories from M(n1) to M(ni), it can be determined and detected that data exists in the memory block n.

公开(公告)号：JP2000132978A

公开(公告)日：2000-05-12

申请号：JP30812198

申请日：1998-10-29

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C7/00 ,  G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To speed up a memory and reduce a consumption power by setting a first and a second switches which are turned on and off between an invertor output and a bit line in accordance with a signal on a word line and, a third and a fourth switches which are turned on and off between the bit line and a bit match node in accordance with an invertor output signal. SOLUTION: A voltage amplitude of a word match line 20 is restricted in a range between a higher potential by a threshold voltage of a PMOS transistor with a back gate bias from a ground potential and a lower potential by a threshold of an NMOS transistor NC: 41 with a back gate bias from a power source potential. The range can be made smaller. Accordingly, the voltage amplitude of the word match line 20 becomes small and a consumption power is reduced. When a precharge potential of the word match line 20 is lowered, boosting a bit line is eliminated although the NMOS transistor is used and a high-speed performance is ensured.

公开(公告)号：JPH1166839A

公开(公告)日：1999-03-09

申请号：JP21275897

申请日：1997-08-07

Applicant: IBM

Inventor： TANAKA MASAHIRO ,  MIYATAKE HISATADA ,  MORI YOTARO ,  YAMAZAKI NORITOSHI

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41

Abstract: PROBLEM TO BE SOLVED: To improve a data transfer rate by transferring data plural times in one memory cycle. SOLUTION: A bit line of a memory array l is grouped based on a remainder when the row addresses are divided by the number of groups, and a row address decoding part 4 composing a bit line selection means 3 generates row addresses of the number corresponding to the number of groups according to the row address signal and an access order signal showing the order of the access to the group, and those bit lines are selected by a bit switch 5. Plural latch parts 6a, 6b, 6c each is provided for each group, and the bit line selection means 3 generates plural row addresses consecutive in the same direction referring to the row address signal corresponding to the access order signal.

公开(公告)号：JP2000137989A

公开(公告)日：2000-05-16

申请号：JP30813198

申请日：1998-10-29

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C7/06 ,  G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To provide a high speed and low power consumption single signal detection circuit (sense amplifier circuit). SOLUTION: In the sense amplifier circuit for detecting/amplifying a signal on a signal line, an inverter pair 11, 12 connecting an output of an inverter to an input of the other side inverter each other and sensing switches being first, second switches 13, 14 connected to source ends of respective inverters of the inverter pair and a constant current source 15, and that the signal line 10 is connected to the first switch, and reference potential Vref is connected to the second switch are incorporated, and the drive force of the first switch is made larger than the same of the second switch.

公开(公告)号：JPH10241399A

公开(公告)日：1998-09-11

申请号：JP3608898

申请日：1998-02-18

Applicant: IBM

Inventor： KALTER HOWARD L ,  JOHN EDWARD BASS JR ,  JEFFREY HARRIS DOREIBERUBISU ,  REX NUGO KOO ,  MORI YOTARO ,  JOHN STEWART PARENTEU JR ,  DONALD LAURENCE WEETER

IPC: G01R31/28 ,  G06F11/273 ,  G11C29/02 ,  G11C29/12 ,  G11C29/32 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a built-in self test BIST macro of a processor base for testing a dynamic random access memory(DRAM) built in a logic chip. SOLUTION: A BIST macro 200 is provided with two ROMs in a sequencer 205, a first ROM is made a ROM for storing a test instruction, a second ROM is made a ROM for scanning, so as to perform sequencing of a test instruction stored in the first ROM as well as a branching function and a loop function. Further, the BIST macro 200 monitors obstacle in a DRAM, and is provided with a redundant allotting logic section 260 for exchanging an obstacle word line or a data line, or the both.

公开(公告)号：JP2000228090A

公开(公告)日：2000-08-15

申请号：JP2831599

申请日：1999-02-05

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C8/08 ,  G11C7/12 ,  G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To reduce average power consumption in search operation of CAM without affecting performance of CAM. SOLUTION: Relating to each word accompanying bits (valid bit) indicating whether data of at the word is valid or not in CAM, a circuit is constituted so that when a valid bit indicates that the word is invalid, pre-charge is controlled so that pre-charge of a match line of the word is prohibited, and a match line is forcedly in a 'uncoincidence state'. Thereby, power consumption caused by search operation by a data word being not a search object is prevented, and power consumption of search operation of the whole CAM is reduced.

公开(公告)号：JPH11213700A

公开(公告)日：1999-08-06

申请号：JP1657598

申请日：1998-01-29

Applicant: IBM

Inventor： KALTER HOWARD L ,  JOHN EDWARD BASS JR ,  JEFFREY HARRIS DOREIBERUBISU ,  REX NUGO KOO ,  MORI YOTARO ,  JOHN STEWART PARENTEU JR ,  DONALD LAURENCE WEETER

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12

Abstract: PROBLEM TO BE SOLVED: To provide a built-in self inspection(BIST) for a processor base for testing a dynamic random access memory(DRAM) built in a logic chip. SOLUTION: A BIST 200 has two ROMs(read only memories) in a sequencer 205. One is to store test commands and the other is a ROM that can be scanned and provides not only a branch function and a loop function, but sequencing of test commands stored in the first ROM. A BIST macro has further a redundant allocation logic section 260 which monitors faults in a DRAM and exchanges a fault word line or a fault data line or both lines.