公开(公告)号：JP2005167589A

公开(公告)日：2005-06-23

申请号：JP2003403371

申请日：2003-12-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MUNETO SEIJI ,  MARUYAMA HIROSHI ,  SELIGER FRANK ,  NAGARATNAM NATARAJ

IPC: G06F12/14 ,  G06F15/00 ,  G06F21/00 ,  G06F21/20 ,  H04L9/32 ,  H04L12/24 ,  H04L29/06

CPC classification number: G06F21/52 ,  G06F21/57 ,  H04L63/123

Abstract: PROBLEM TO BE SOLVED: To provide an information processing unit and a method therefor, a server unit and a method therefor, and a unit mountable program. SOLUTION: The information processing unit uses a conformity value with signatures that is inherent to a software configuration and assures conformity in the initial code of a server connected to a network. The server unit generates keys for certifying the server unit (S810, S820, S830). One of the keys is certified by a third party and generates a handwoven, digital signature (S840). The digital signature is added to a conformity value, and the conformity value having signatures is communicated to the information processing unit, thus enabling the information processing unit to receive safe service via a network (S850, S860). COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种信息处理单元及其方法，服务器单元及其方法以及单元安装程序。 解决方案：信息处理单元使用具有软件配置固有的签名的一致性值，并确保连接到网络的服务器的初始代码中的一致性。 服务器单元产生用于认证服务器单元的键（S810，S820，​​S830）。 其中一个钥匙由第三方认证，并生成手工编织的数字签名（S840）。 将数字签名添加到一致性值，并且具有签名的一致性值被传送到信息处理单元，从而使信息处理单元能够经由网络接收安全服务（S850，S860）。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH10269164A

公开(公告)日：1998-10-09

申请号：JP4908998

申请日：1998-03-02

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  STEPHEN VICTOR KOSONOKKII ,  MUNETO SEIJI

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06T1/20 ,  G06T1/60 ,  G09G5/39 ,  H04N7/26 ,  H04N7/50

Abstract: PROBLEM TO BE SOLVED: To solve the problems of fractionization of the computer system and memory bandwidth by an improved method, by connecting a memory chip, which has a bus interface built in a memory chip to an existing connection point of the computer system. SOLUTION: Such a memory 63 is necessary that includes main constituent elements to sufficient density for a main memory and a frame buffer and has a bus interface(I/F) 631, an on-chip data centralized computing function 623, and an optional RAM digital-to-analog converting(DAC) function 633 integrated. For the memory 63, architectures are arranged so as to shorten a wait time and improve data bandwidth. The data centralized computing function 632 functions for motion compensation, etc., in bit block transfer, rendering, z- comparison, alpha blending, MPEG(motion picture expert group) encoding for efficient image hierarchical constitution.

公开(公告)号：JPH09160723A

公开(公告)日：1997-06-20

申请号：JP31779795

申请日：1995-12-06

Applicant: IBM JAPAN

Inventor： MUNETO SEIJI ,  NIIJIMA HIDETO ,  MURATA HIROKI ,  TAKAHASHI NOBUAKI

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10

Abstract: PROBLEM TO BE SOLVED: To prevent a data storage system from being complicated by transferring fast the data via data buses and also facilitating the control of the timing of the system. SOLUTION: The mutual synchronization of accesses is secured among storage means 13 to 17 which store the data. For this purpose, the data buses 11 and 12 are prepared to transfer the data together with an input/output means 21 which transfers the plural data series to the buses 11 and 12 with interleave, and a latch means 23 which is provided at plural stages and in series between the means 13 to 17 and the buses 11 and 12 and hold the data respectively.

公开(公告)号：JPH08202497A

公开(公告)日：1996-08-09

申请号：JP1043595

申请日：1995-01-26

Applicant: IBM JAPAN

Inventor： MUNETO SEIJI ,  NIIJIMA HIDETO ,  MURATA HIROKI ,  TAKAHASHI NOBUAKI

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16

Abstract: PURPOSE: To facilitate transfer operation and restore data efficiently at a high speed in the case of fault occurrence by providing plural storage means, a data bus, and a selecting means having a function for parity arithmetic operation. CONSTITUTION: Two channels of 4-channel crossbar switches 11a and 11b having an exclusive OR operation function are connected to data buses DDO and DD1 as common buses. Other two channels of the crossbar switch 11a as the selecting means are connected to drives HDDO and HDD1. Other two channels of the crossbar switch 11b are connected to drives HDD2 and HDD3. Further, the crossbar switches 11a and 11b are controlled with an address signal and a control signal outputted from a data bus controller 13, and connections in optional combinations of drives and data buses are enabled. Thus, the selecting means itself is provided with the function for parity arithmetic operation.