公开(公告)号：JP2001101787A

公开(公告)日：2001-04-13

申请号：JP27332699

申请日：1999-09-27

Applicant: IBM

Inventor： KURODA TAKASHI ,  KIGAMI YUJI ,  MURAKAMI MASAYUKI

IPC: G06F3/06 ,  G11B20/10 ,  G11B20/12

Abstract: PROBLEM TO BE SOLVED: To enhance the performance of the disk drive device by reducing the time required to expand track information to its memory. SOLUTION: The disk drive device is provided with a disk 35 that stores user data, a controller (HDC and MPU 21) that control read/write of the user data to/from this disk 35 and generates track information for the disk 35, and a memory (DRAM 32) that stores the user data to be read/written from/to the disk 35 and stores the track information generated by the controller (HDC and MPU 21) as well. This controller (HDC and MPU 21) transfers the generated track information to the memory (DRAM 32) by using a drive data bus 26 that transfers the user data.

公开(公告)号：JPH08293802A

公开(公告)日：1996-11-05

申请号：JP8850495

申请日：1995-04-13

Applicant: IBM

Inventor： NAKAMURA AKIO ,  MURAKAMI MASAYUKI ,  NUMATA TSUTOMU

IPC: H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H03M13/22

Abstract: PURPOSE: To correct further large amounts of errors by suppressing the increase of a check symbol part to the absolute minimum, and unnecessitating error position information from the outside by operating encoding by a crossing method using two codes whose design distance is different. CONSTITUTION: An encoder 12 of a device 10 converts a digital data input into the stream of symbols being the constituting elements of a code word, the re-arrangement of a sequence is executed by an interleave controller 14, and a code part is calculated for each system. Then, an individual system in which information blocks are crossed by a crossing method is obtained. One system is selected from among (k) pieces of systems, and a check symbol which is longer than that of the other systems is added to the selected system. As a result, one system whose design distance is (d2 +1) and (k-1) pieces of systems whose design distance is (d2 +1) are formed. When correctable continuous errors with less than length (t)1 are detected in the decoding process of the system 1, it is assumed that an error is generated at the adjacent code position in the other system, and this adjacent position is defined as an annihilation trace and handled in the following processing.

公开(公告)号：JPH0816321A

公开(公告)日：1996-01-19

申请号：JP14825594

申请日：1994-06-29

Applicant: IBM

Inventor： ASANO HIDEO ,  MURAKAMI MASAYUKI

IPC: G06F13/10 ,  G06F3/06

Abstract: PURPOSE: To control an interruption request asserted to a host on pre-reading, post-reading and both reading. CONSTITUTION: The resetting state of a flip flop 72 is maintained and IRQ is prevented from being asserted by a host until the count value of a counter 80 becomes equal to the content of delay register 82. When the read signal of a state register is inputted to a flip flop 78 through an OR gate 94 until the count value of the counter 80 becomes equal to the content of the delay register 82, the flip flop 78 is set and Q output is maintained high as it is as post-reading and both reading. When the count value of the counter 80 becomes equal to the content of the delay register 82, the output of a comparator 84 becomes low, the flip flop 72 is set and IRQ is asserted by the host with CDR.