3.
    发明专利
    未知

    公开(公告)号:DE10050171B4

    公开(公告)日:2006-01-05

    申请号:DE10050171

    申请日:2000-10-11

    Applicant: IBM

    Abstract: A system and method are provided that reduce the amount of data held commonly in both high-ranking and low-ranking cache memories, thereby having each of those cache memories hold data more efficiently. More particularly, a computer system is provided with an HDC card 21 connected to an expansion bus 20 and an HDD unit 22 connected to the HDC card 21. The HDC card 21 is provided with a disk cache (high-ranking cache memory) and the HDD unit 22 is provided with a disk cache 54 (low-ranking cache memory). The HDC card 21 and the HDD unit 22 exchange select information for selecting a swap mode of each cache memory when the system is started up, thereby selecting different swap modes according to the exchanged select information respectively.

    6.
    发明专利
    未知

    公开(公告)号:DE3575510D1

    公开(公告)日:1990-02-22

    申请号:DE3575510

    申请日:1985-09-24

    Applicant: IBM

    Abstract: The bi-level image data supplied from an image supply means, such as an image scanner are pre-processed by the present invention, and the pre-processed image data are then supplied to a compression means, which compresses the image data under a conventional two-dimensional coding scheme, e.g. such as provided by the CCITT Recommendation T.4. The pre-process detects (3, 4, 5) a changing element in a first scan line and a changing element in a second scan line. It then determines (6, 7) whether the distance between the changing element in the first scan line and the changing element in the second scan line is falling within a predetermined range. The image data are re-arranged (8, 9, 10) so as to decrease the said distance to a predetermined smaller value when the distance is falling within the said predetermined range, and otherwise are preserved unchanged. The rearranged and the otherwise preserved image data are then supplied (11) to means for performing the compression.

    METHOD FOR PROCESSING BI-LEVEL IMAGE DATA

    公开(公告)号:CA1262279A

    公开(公告)日:1989-10-10

    申请号:CA484634

    申请日:1985-06-20

    Applicant: IBM

    Abstract: The invention discloses a method for processing bi-level image data supplied from an image supply means, said bi-level image data being compressed under a two-dimensional coding scheme, comprising the steps of detecting a changing element in the first scan line and a changing element in the second scan line, determining whether a distance between said changing element in said first scan line and said changing element in said second scan line has fallen within a predetermined range, re-arranging said image data to decrease said distance to a predetermined distance when said distance has fallen within said predetermined range, and supplying said re-arranged image data to means for performing said compression.

    Method for executing an error recovery procedure

    公开(公告)号:SG74027A1

    公开(公告)日:2000-07-18

    申请号:SG1997003791

    申请日:1997-10-18

    Applicant: IBM

    Abstract: An error recovery procedure (ERP) in a storage device such as a rotating magnetic hard disk drive is executed to the last step regardless of the established time-out period for an instruction, thereby more reliably recovering from errors. In accordance with one embodiment of the invention, when a disk drive receives a reset instruction from a host during the execution of an ERP, it executes the ERP until the error is recovered, or to the last step without interrupting the ERP. Further, in accordance with another embodiment of the invention, when a disk drive receives a reset instruction during the execution of an ERP, it stops execution of the ERP and holds the number K of the step which was completed immediately before stopping, and when receiving a retry instruction after that, sequentially executes the ERP from the K+1-th error recovery step.

    10.
    发明专利
    未知

    公开(公告)号:DE69316323D1

    公开(公告)日:1998-02-19

    申请号:DE69316323

    申请日:1993-10-04

    Applicant: IBM

    Abstract: To provide an interface circuit which performs data transfer surely without a wasteful waiting time with the same hardware, whether the status reading by a host is performed before or after the data transfer. The interface circuit comprises interrupt means (60) for generating an interrupt request (IRQ) to a host (12) in response to a data request (DRQ) from a peripheral device (HDD) and dropping the interrupt request if the status of the peripheral device is read by the host, mode detecting means (62) for detecting that the host operates in a post-read mode, and interrupt enable means (64) responsive to the post-read mode detect signal from the mode detecting means and the status reading by the host to enable the interrupt means to regenerate the interrupt request to the host.

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