公开(公告)号：JPH06214934A

公开(公告)日：1994-08-05

申请号：JP30835392

申请日：1992-11-18

Applicant: IBM

Inventor： KIGAMI YUJI ,  NUMATA TSUTOMU ,  SAKAI TATSUYA ,  SHIMIZU KENJI

IPC: G06F3/06 ,  G06F9/445 ,  G06F13/12 ,  G06F13/38

Abstract: PURPOSE: To provide a programmable storage controller which can minimize the intervention of a microprocessor and also excels in both extendibility and flexibility. CONSTITUTION: This controller includes a buffer 16 which stores a data transfer control program in addition to the data that are transferred between a host 10 and an external storage 14, a controller 18 which reads the data transfer control program out of the buffer 16 and carries it out, and a microprocessor 20 which starts to read the program out of the buffer 16 and to send it to the controller 18 in response to the command given from the host 10. The controller 18 controls the data that are transferred between the host 10 and the storage 14 independently of the microporcessor 20. Meanwhile, the processor 20 can carry out other jobs.

公开(公告)号：JPH0945023A

公开(公告)日：1997-02-14

申请号：JP19010995

申请日：1995-07-26

Applicant: IBM

Inventor： OGASAWARA KENJI ,  NAKAMURA TAKASHI ,  MATSUBARA NOBUYA ,  NAKAGAWA YUZO ,  KIGAMI YUJI ,  UCHIIKE HIROSHI ,  NUMATA TSUTOMU

IPC: G11B21/10 ,  G11B5/55 ,  G11B5/596 ,  G11B21/08

Abstract: PROBLEM TO BE SOLVED: To prevent servo information from being reproduced of error and to form correct servo information, by providing a plurality of bit patterns which are not prevent principally in other servo areas than a servo start mark SSM. SOLUTION: A cylindrical support 16 is set to a shaft 12, with having one or more data-recording discs 18A, 18B loaded at an outer peripheral face thereof. A data area 52 is formed in each recording face of the discs 18A, 18B. Servo areas 50 are radially formed in the data area. A start position of the servo area is indicated by a servo start mark SSM. A plurality of bit patterns in the signal SSM are constituted so as not to be read in other servo areas, i.e., a gray code area, a sector area and a position error signal PES area. Therefore, the SSM signal is never read out in the other servo areas, and reading errors and prevented.

公开(公告)号：JPH03134732A

公开(公告)日：1991-06-07

申请号：JP26798689

申请日：1989-10-17

Applicant: IBM

Inventor： NUMATA TSUTOMU ,  OGAKI KAZUTAKA ,  YAMAGUCHI MARIO

IPC: G06F5/14 ,  G06F5/10

Abstract: PURPOSE: To improve the utilization efficiency of a buffer by writing data in an area where the data are not stored regardless of the size relation of the value of a write pointer and the value of a read pointer. CONSTITUTION: The write pointer for specifying a write address and the read pointer for specifying a read address are provided and the value of the write pointer and the value of the read pointer are compared at all times in a comparator 5. Then, when the value of the write pointer and the value of the read pointer match, a pointer which caught up later is discriminated by a discrimination circuit 6 and an auxiliary discrimination circuit 13, write to the buffer is inhibited at the time of discriminating that the write pointers caught up later and read from the buffer is inhibited at the time of discriminating that the read pointer caught up later inversely. Thus, the buffer is effectively utilized.

公开(公告)号：JPH08293802A

公开(公告)日：1996-11-05

申请号：JP8850495

申请日：1995-04-13

Applicant: IBM

Inventor： NAKAMURA AKIO ,  MURAKAMI MASAYUKI ,  NUMATA TSUTOMU

IPC: H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H03M13/22

Abstract: PURPOSE: To correct further large amounts of errors by suppressing the increase of a check symbol part to the absolute minimum, and unnecessitating error position information from the outside by operating encoding by a crossing method using two codes whose design distance is different. CONSTITUTION: An encoder 12 of a device 10 converts a digital data input into the stream of symbols being the constituting elements of a code word, the re-arrangement of a sequence is executed by an interleave controller 14, and a code part is calculated for each system. Then, an individual system in which information blocks are crossed by a crossing method is obtained. One system is selected from among (k) pieces of systems, and a check symbol which is longer than that of the other systems is added to the selected system. As a result, one system whose design distance is (d2 +1) and (k-1) pieces of systems whose design distance is (d2 +1) are formed. When correctable continuous errors with less than length (t)1 are detected in the decoding process of the system 1, it is assumed that an error is generated at the adjacent code position in the other system, and this adjacent position is defined as an annihilation trace and handled in the following processing.

公开(公告)号：JPH10269676A

公开(公告)日：1998-10-09

申请号：JP6879197

申请日：1997-03-21

Applicant: MITSUBISHI ELECTRIC CORP ,  IBM

Inventor： ITO SAKAE ,  SAKAI TATSUYA ,  MURAKAMI MASAYUKI ,  NUMATA TSUTOMU

IPC: G11B19/00 ,  G06F3/06 ,  G11B19/02

Abstract: PROBLEM TO BE SOLVED: To accelerate an input/output of the data by continuously, discretely or continuous/concrete mixedly performing plural times of data inputs/outputs with a hard disk controller by a once access request command imparted from a CPU at an optional access time at every time according to a response status generated from a control resource access condition. SOLUTION: The timing outputting a response status signal (ACK) is decided by a processing state of a hard disk controller(HDC) 34, and the matter that an access time of a microcomputer unit(MCU) 33 is extended is possible. Since the MCU 33 is clock synchronized with the HDC 34, the resource accessible in a short time such as a register on the HDC 34 is transferred in a short time without a delay of the ACK. In the case of continuous access, though a head address of an access request signal is outputted from the MCU 33, a succeeding address is generated by an addition circuit in the HDC 34.

公开(公告)号：DE69325774T2

公开(公告)日：2000-03-02

申请号：DE69325774

申请日：1993-11-09

Applicant: IBM

Inventor： NUMATA TSUTOMU ,  KIGAMI YUJI ,  SAKAI TATSUYA ,  SHIMIZU KENJI

IPC: G06F3/06 ,  G06F9/445 ,  G06F13/12 ,  G06F13/38 ,  G06F9/44

Abstract: A programmable external storage control apparatus is provided which requires minimum intervention of a microprocessor and has more extendibility and flexibility. It includes a buffer (16) which stores a data transfer control program in addition to data to be transferred between a host (10) and an external storage (14), a controller (18) which reads from the buffer (16) and executes the data transfer control programs, and a microprocessor (20) which starts reading of the program from the buffer (16) to the controller (18) in response to a command from the host (10). The controller (18) controls data transfer between the host and the external storage independently of the microprocessor (20) while the microprocessor (20) may execute other jobs.

公开(公告)号：JPH10214201A

公开(公告)日：1998-08-11

申请号：JP1574397

申请日：1997-01-29

Applicant: MITSUBISHI ELECTRIC CORP ,  MITSUBISHI DENKI SYS LSI DES ,  IBM

Inventor： ITO SAKAE ,  KANZAKI TERUAKI ,  AKATSUKI TADAYUKI ,  SAKAI TATSUYA ,  NUMATA TSUTOMU ,  NAKAMURA YASUHIRO

IPC: G06F11/28 ,  G06F9/06 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To obtain a microcomputer in which a debug circuit equipped with various functions used at the time of program debugging is provided in the microcomputer, and a flash memory electrically capable of writing/erasing incorporated on the same chip can be used as an emulation memory. SOLUTION: This device is provided with a flash memory 6 electrically capable of writing/erasing in which a program in a development stage is stored and a debug circuit 7 having an exclusive input and output terminal 8 for connection with an outside ICE are incorporated in this device. The debug circuit 7 is provided with a communicating function with a CPU 1, a communicating function with the ICE, the trace function of the operating state of the CPU 1, break function for generating debug interruption, function for writing a program code from the ICE in the flash memory 6, and function for transmitting the content of the flash memory 6 to the ICE.

公开(公告)号：JPH07211000A

公开(公告)日：1995-08-11

申请号：JP31878093

申请日：1993-12-17

Applicant: IBM

Inventor： KIGAMI YUJI ,  YOKOE YUJI ,  NUMATA TSUTOMU ,  NAKAMURA TAKASHI ,  OGASAWARA KENJI ,  KURACHI KOJI ,  MATSUI TAKAO ,  OKADA MAYUMI

IPC: G11B20/10 ,  G11B5/012 ,  G11B5/09 ,  G11B19/02 ,  G11B20/12 ,  G11B20/18 ,  G11B27/10

Abstract: PURPOSE: To refer to information on constitution or the like for respective sectors and to increase information quantity by permitting a hard disk controller to calculate an absolute block address to calculate a physical position in a specified zone and executing a seek operation based on the physical position. CONSTITUTION: The hard disk controller HDC 30 refers to a defect list D-LST and calculates the absolute block address ABA by all the sectors, which corresponds to a designated logic block address LBA. When a host computer requests the reading of the sectors from #L to #M in the address LBA, the absolute block address ABA is calculated to be #N. When the belonging zone Zn is set to be #Z, the min address ABA is to be MIN-ABBA(#Z) and a min cylinder is MIN-CYL(#Z), the address ABA is shown by an expression. Then, #ZN is set to be the serial numbers of the sectors. The head is switched and the seek operation is executed based on the physical position which is thus calculated.

公开(公告)号：JPH0384767A

公开(公告)日：1991-04-10

申请号：JP21619889

申请日：1989-08-24

Applicant: IBM

Inventor： NAKAGAWA YOSHIHIRO ,  NUMATA TSUTOMU ,  OGAKI KAZUTAKA

IPC: G06F3/06 ,  G11B5/596 ,  G11B27/10

Abstract: PURPOSE: To shorten a track changeover time and to reduce a processor load by providing a head position control means by which a final sector indication means completes an access of a head to a detected track, according to the final sector detection signal. CONSTITUTION: A final sector of each track on a disk is provided with a final sector indication means. In a device which performs positioning control of a head 6 onto a disk 2 under a control of a processor 10 like, for example, a mask processor, the processor 10 can complete an access of the head 6 to a track of which a final sector has been detected, by inputting the detected signal for the final sector indication means to the processor 10 as an interrupt signal. Also, it can make the head 6 move to the next target track. Consequently, when reading or writing is performed over multiple tracks, a track changeover time can be shorten and, as a result, a processor load can be reduced.

公开(公告)号：JPH02158824A

公开(公告)日：1990-06-19

申请号：JP31204088

申请日：1988-12-12

Applicant: IBM JAPAN

Inventor： NAKAMURA TAKASHI ,  NUMATA TSUTOMU ,  OGAKI KAZUTAKA

IPC: G06F3/06

Abstract: PURPOSE:To effectively use the memory of a disk device by providing a shared storing means to write outputted data in conformity to prescribed preferential order and time division multiplex controlling means to read the stored data in conformity to the prescribed preferential order. CONSTITUTION:One storing means 10 is shared by a microprocessor 6, host computer 4 and the disk device 12, and the data to be outputted from the microprocessor 6, the host computer 4 and the disk device 12 is written in the shared storing means 10 in conformity to the prescribed preferential order. Then, the time division multiplex controlling means 8 to read the data stored in the shared storing means 10 to the microprocessor 6, the host computer 4 and the disk device 12 in conformity to the prescribed preferential order is provided. Namely, a memory function to store the data to be used by the microprocessor 6 to control the disk device 12 and the function to transfer the data between the disk device 12 and the host computer 4 are given to one storing means 10. Thus, the memory of the disk device 12 can be used effectively.