公开(公告)号：JP2001101764A

公开(公告)日：2001-04-13

申请号：JP27412999

申请日：1999-09-28

Applicant: IBM

Inventor： TAKASE YASUHIRO ,  MURAKAMI MASAYUKI ,  KANAI TOSHIO

IPC: G06F1/32 ,  G06F1/04 ,  G11B19/00 ,  H03K17/22 ,  H03K19/003

Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of an electronic circuit to operate based on a clock signal when the power is applied. SOLUTION: The power consumption reduction circuit 40 is provided with a clock frequency reduction circuit 41. When a received POR signal is asserted, the clock frequency reduction circuit 41 decreases the frequency of a received CK signal and outputs the CK signal to an IC selection circuit 42. When the received POR is negated, the clock frequency reduction circuit 41 outputs the received CK signal to the IC selection circuit 42 as it is. The signal outputted from the clock frequency reduction circuit 41 is fed to a plurality of ICs 51, 52,..., IC 53 via the IC selection circuit 42.

公开(公告)号：JP2000155751A

公开(公告)日：2000-06-06

申请号：JP32832898

申请日：1998-11-18

Applicant: MITSUBISHI ELECTRIC CORP ,  IBM

Inventor： UEKI HIROSHI ,  ITO SAKAE ,  SAKAI TATSUYA ,  MURAKAMI MASAYUKI

IPC: G06F9/32 ,  G06F3/06 ,  G06F9/38 ,  G06F12/00 ,  G06F13/28 ,  G06F15/78 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To enable CPU of an MPU to read a program code out of the memory of a control LSI fast by incorporating in the control LSI a code interface circuit which supplies the program code stored in the memory to the CPU. SOLUTION: The CPU 3 of the MPU 1 outputs a branch request signal RCLR and a branch address AD-CPU to both CIU 4 and CIU 21 at a program address branch time. The CIU 4 and CIU 21 once receiving the branch address AD-CPU decode the branch address AD-CPU and decide whether the address is in address ranges assigned to themselves. The CIU 21 outputs the value of the branch address AD-CPU to the address bus of HDC 2 when the value of the branch address AD-CPU is in its address range. The CIU 21 supplies the program code to the CPU 3 independently of 'code prefetching operation'.

公开(公告)号：JPH1166695A

公开(公告)日：1999-03-09

申请号：JP21864197

申请日：1997-08-13

Applicant: IBM

Inventor： SAKAI TATSUYA ,  MURAKAMI MASAYUKI ,  KAGAMI NAOYUKI ,  NAKAGAWA YUZO

IPC: G11B21/10 ,  G11B5/596 ,  G11B19/02

Abstract: PROBLEM TO BE SOLVED: To reduce a processing load of an MPU without increasing costs so much and to easily realize an advanced servo control. SOLUTION: Reproduced levels A, B, C and D of respective burst patterns from a channel 5 is subject to an AD conversion by ADC(A/D converter) 16 and are set to an ADC REG(ADC register) 17. A parameter such as a position error of a head 2 is obtained, independent on an MPU 12, by an SA 23 in accordance with the reproduced levels of the respective burst patterns held in the ADC REG 17 and instructions from the MPU 12, etc., held in an SRAM 24, survo data (DACOUT) for driving a VCM(voice.coil.motor) are computed in accordance therewith and are supplied to a DAC of a VCM driving part 6 via an SIO 22.

公开(公告)号：DE69316323D1

公开(公告)日：1998-02-19

申请号：DE69316323

申请日：1993-10-04

Applicant: IBM

Inventor： ASANO HIDEO ,  MURAKAMI MASAYUKI

IPC: G06F3/06 ,  G06F13/10 ,  G06F13/12 ,  G06F13/38

Abstract: To provide an interface circuit which performs data transfer surely without a wasteful waiting time with the same hardware, whether the status reading by a host is performed before or after the data transfer. The interface circuit comprises interrupt means (60) for generating an interrupt request (IRQ) to a host (12) in response to a data request (DRQ) from a peripheral device (HDD) and dropping the interrupt request if the status of the peripheral device is read by the host, mode detecting means (62) for detecting that the host operates in a post-read mode, and interrupt enable means (64) responsive to the post-read mode detect signal from the mode detecting means and the status reading by the host to enable the interrupt means to regenerate the interrupt request to the host.

公开(公告)号：JPH05233513A

公开(公告)日：1993-09-10

申请号：JP33799591

申请日：1991-11-28

Applicant: IBM

Inventor： MURAKAMI MASAYUKI ,  SAITO HIROSHI ,  IWASA HIROYUKI

IPC: G06F13/12 ,  G06F13/24

Abstract: PURPOSE: To provide an interface circuit executing data transfer without error by means of the same hardware whatever mode a host is in. CONSTITUTION: In a computer system including a pre-reading mode starting block data transfer after reading the situation of the pertinent device in response to interruption from a peripheral device (HD) or a host reading the situation after finishing block data transfer, the interface is provided with a mode detection means 60 automatically detecting which mode the host is operated in order to execute data transfer without an error between the peripheral device and the host whatever mode the host is in, a delay means 62 delaying a data request DRQ showing block data transfer preparation is finished when a post-reading mode is detected by a prescribed time, and an interruption means 64 sending an interruption request IRQ to the host in response to the output of this delay means.

公开(公告)号：JP2008226280A

公开(公告)日：2008-09-25

申请号：JP2008166411

申请日：2008-06-25

Applicant: Internatl Business Mach Corp ,  Renesas Technology Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ルネサステクノロジ

Inventor： UEKI HIROSHI ,  ITO SAKAE ,  SAKAI TATSUYA ,  MURAKAMI MASAYUKI

IPC: G06F12/06

Abstract: PROBLEM TO BE SOLVED: To obtain a system LSI for enabling a control LSI to read data from a memory of an MPU at a high speed.
SOLUTION: When a control circuit outputs an address and a read access request signal, the address is decoded, when the address is an address within an area of the memory, the address and the read access request signal are outputted to a data interface circuit, and an access circuit for acquiring data from the data interface circuit is incorporated in the control LSI.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：获得用于使控制LSI能够高速地从MPU的存储器读取数据的系统LSI。 解决方案：当控制电路输出地址和读取访问请求信号时，地址被解码，当地址是存储器区域内的地址时，地址和读取访问请求信号被输出到数据 接口电路和用于从数据接口电路获取数据的访问电路并入控制LSI中。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JPH10269676A

公开(公告)日：1998-10-09

申请号：JP6879197

申请日：1997-03-21

Applicant: MITSUBISHI ELECTRIC CORP ,  IBM

Inventor： ITO SAKAE ,  SAKAI TATSUYA ,  MURAKAMI MASAYUKI ,  NUMATA TSUTOMU

IPC: G11B19/00 ,  G06F3/06 ,  G11B19/02

Abstract: PROBLEM TO BE SOLVED: To accelerate an input/output of the data by continuously, discretely or continuous/concrete mixedly performing plural times of data inputs/outputs with a hard disk controller by a once access request command imparted from a CPU at an optional access time at every time according to a response status generated from a control resource access condition. SOLUTION: The timing outputting a response status signal (ACK) is decided by a processing state of a hard disk controller(HDC) 34, and the matter that an access time of a microcomputer unit(MCU) 33 is extended is possible. Since the MCU 33 is clock synchronized with the HDC 34, the resource accessible in a short time such as a register on the HDC 34 is transferred in a short time without a delay of the ACK. In the case of continuous access, though a head address of an access request signal is outputted from the MCU 33, a succeeding address is generated by an addition circuit in the HDC 34.

公开(公告)号：JPH06259196A

公开(公告)日：1994-09-16

申请号：JP4405193

申请日：1993-03-04

Applicant: IBM

Inventor： ASANO HIDEO ,  SHIMOMURA KEISUKE ,  MURAKAMI MASAYUKI

IPC: G06F3/06 ,  G06F13/14 ,  G06F13/40 ,  G11B33/06

Abstract: PURPOSE: To designate two disk driving devices connected with an AT interface as a master or a slave in local selection or cable selection only by one jumper block. CONSTITUTION: This is a disk driving device connected through plural interface lines including one interface line connected with a first voltage level of a data processor with the data processor. This device includes plural connecting points connected with the plural interfaces lines, first connecting point selectively connected with one interface line, second connecting point which is held in a floating voltage, third connecting point connected with the first voltage level, fourth connecting point connected with a second voltage level, and selectively connected with one of the first, second, and third connecting points, a controller connected with the fourth connecting point which detects the voltage level of the fourth connecting point, and recognizes itself as a first disk driving device or a second disk driving device.

公开(公告)号：JP2001282541A

公开(公告)日：2001-10-12

申请号：JP2000089860

申请日：2000-03-28

Applicant: IBM

Inventor： MURAKAMI MASAYUKI ,  TAKASE YASUHIRO ,  SAKAI TATSUYA

IPC: G06F3/06 ,  G06F9/445

Abstract: PROBLEM TO BE SOLVED: To easily change a microcode in a control element using a system LSI forming a DRAM in the same chip substrate without generating a production lead time and requiring the reevaluation of the LSI. SOLUTION: A semiconductor device 10 connecting its terminal 17 to an external serial ROM 11 is provided with a DRAM 14 formed on the same chip substrate, a comparator 20 for inputting data of one byte from the terminal 17 and comparing whether the data is 'FF' or '00' (both of which are hexadecimal numbers) or not and a selector 18 for selecting download from an internal serial mask ROM 19 when the compared result is true or selecting download from the external serial ROM 11 when the compared result is false. The downloaded program is recorded in the DRAM 14.

公开(公告)号：JPH06139176A

公开(公告)日：1994-05-20

申请号：JP26437192

申请日：1992-10-02

Applicant: IBM

Inventor： ASANO HIDEO ,  MURAKAMI MASAYUKI

IPC: G06F3/06 ,  G06F13/10 ,  G06F13/12 ,  G06F13/38

Abstract: PURPOSE: To provide an interface circuit by which data transfer is executed with the same hardware correctly without useless waiting time independently of whether conditions are read by a host before or after the data transfer. CONSTITUTION: This circuit is provided with a means 60 for generating an interruption request(IRQ) to a host 12 in response to a data request(DRQ) at a peripheral device(HDD) and canceling the IRQ when the host reads the conditions of the HDD, a mode detecting means 62 for detecting the operation of the host in a post-reading mode, and an interruption energizing means 64 for generating the IRQ to the host again by energizing an interrupting means in response to a post-reading mode detecting signal from the mode detecting signal and the reading of conditions due to the host.