公开(公告)号：JPH04328665A

公开(公告)日：1992-11-17

申请号：JP11669491

申请日：1991-04-22

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  OBA NOBUYUKI ,  NAKADA TAKEO

IPC: G06F9/48 ,  G06F9/50 ,  G06F13/24 ,  G06F13/26 ,  G06F13/362

Abstract: PURPOSE: To distribute I/O interruptions to respective processors by arbitrating the interruptions by using parameters showing the load states of the processors as 1st priority PPR and additionally selecting one processor according to 2nd interruption priority RRPR which varies cyclically unless one processor is not determined. CONSTITUTION: Data of PPR 11 and RRPR 12 are temporarily stored in a buffer 15. The PPR 11 specifies the priority of an I/O interruption corresponding to the execution priority of a process and is used for 1st arbitration based upon the execution priority of the process. The RRPR 12 of each interrupt arbiter is a counter which cyclically counts within the range of the number of the processors and initialized to characteristic priority when the system is actuated to have a different value from any other interrupt arbiter. An encoder sends a selected request signal varying in interruption request level to control logic 14, which is actuated to inhibit an arbitration line 4 to a bus arbiter from being used.