公开(公告)号：JPH04328665A

公开(公告)日：1992-11-17

申请号：JP11669491

申请日：1991-04-22

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  OBA NOBUYUKI ,  NAKADA TAKEO

IPC: G06F9/48 ,  G06F9/50 ,  G06F13/24 ,  G06F13/26 ,  G06F13/362

Abstract: PURPOSE: To distribute I/O interruptions to respective processors by arbitrating the interruptions by using parameters showing the load states of the processors as 1st priority PPR and additionally selecting one processor according to 2nd interruption priority RRPR which varies cyclically unless one processor is not determined. CONSTITUTION: Data of PPR 11 and RRPR 12 are temporarily stored in a buffer 15. The PPR 11 specifies the priority of an I/O interruption corresponding to the execution priority of a process and is used for 1st arbitration based upon the execution priority of the process. The RRPR 12 of each interrupt arbiter is a counter which cyclically counts within the range of the number of the processors and initialized to characteristic priority when the system is actuated to have a different value from any other interrupt arbiter. An encoder sends a selected request signal varying in interruption request level to control logic 14, which is actuated to inhibit an arbitration line 4 to a bus arbiter from being used.

公开(公告)号：CA2011503C

公开(公告)日：1994-03-15

申请号：CA2011503

申请日：1990-03-05

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F1/12

Abstract: A number of synchronization controllers are provided for a multiprocessor system, one controller being provided for each processor and all being commonly connected to a synchronization signal bus. Each of these synchronization controllers has a synchronization wait signal transmitting means for receiving a synchronization request signal from a corresponding processor and transmitting a synchronization wait signal to the synchronization signal bus. Each controller also includes: (a) a synchronization register for specifying the other processors to be synchronized with the corresponding processor; (b) a comparator means for comparing the signal from the synchronization signal bus with the content of the synchronization register; and (c) a means for transmitting to the corresponding processor a synchronization-acknowledge signal based on the result of the comparison by the comparator means.

公开(公告)号：DE69030523D1

公开(公告)日：1997-05-28

申请号：DE69030523

申请日：1990-02-23

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F15/16 ,  G06F9/46

Abstract: A multiprocessor system wherein a plurality of processors are connected through a shared data bus, each of the processors generating synchronisation request signals in response to its instruction stream, synchronisation required among processes assigned to the processors being achieved by the synchronisation request signals, wherein indicators signifying the requirement to synchronise are embedded in the processes and there is provided a synchronisation controller to each of the processors; and a synchronisation signal bus to which the synchronisation controllers are commonly connected; and each synchronisation controllers has means for recording which processors are involved in the current process synchronisation, means for broadcasting on the synchronisation bus the current processor status in an individual portion of the communication channel provided thereby, means for snooping the synchronisation bus to monitor the total communication channel and means responsive to such snooping and to the involvement recording means to signal the associated processor that all processors recorded to be involved are indicating the same status. The system can be rendered hierarchical by clustering and can handle pipelined operations.

公开(公告)号：DE69030523T2

公开(公告)日：1997-10-23

申请号：DE69030523

申请日：1990-02-23

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167 ,  G06F15/16 ,  G06F9/46

Abstract: A multiprocessor system wherein a plurality of processors are connected through a shared data bus, each of the processors generating synchronisation request signals in response to its instruction stream, synchronisation required among processes assigned to the processors being achieved by the synchronisation request signals, wherein indicators signifying the requirement to synchronise are embedded in the processes and there is provided a synchronisation controller to each of the processors; and a synchronisation signal bus to which the synchronisation controllers are commonly connected; and each synchronisation controllers has means for recording which processors are involved in the current process synchronisation, means for broadcasting on the synchronisation bus the current processor status in an individual portion of the communication channel provided thereby, means for snooping the synchronisation bus to monitor the total communication channel and means responsive to such snooping and to the involvement recording means to signal the associated processor that all processors recorded to be involved are indicating the same status. The system can be rendered hierarchical by clustering and can handle pipelined operations.

公开(公告)号：JPH02238553A

公开(公告)日：1990-09-20

申请号：JP5776289

申请日：1989-03-13

Applicant: IBM JAPAN

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167

Abstract: PURPOSE:To ensure the effective use of a multiprocessor system for plural applications by transmitting the synchronism satisfaction signals to the corresponding processors based on the result of the comparison carried out between the signal received from a synchronizing signal bus and the contents of a synchronous register. CONSTITUTION:The synchronizing signal lines SL1 - SLn of a synchronizing signal bus 2 are assigned to the processors P1 - Pn respectively. Then the syn chronizing signals Sync are transmitted from the processors P1 - Pn. A compara tor 4 samples the data on the bus 2 for each clock or each half clock and compares them with the data on a synchronous register 3. A timing control circuit 5 receives the signals Sync and returns the signals Sync and Ack accord ing to the clocks. Thus it is possible to attain at a high speed many synchronous states among the processes to which the processors P1 - Pn are assigned and to carry out plural parallel processing programs at the same time.