公开(公告)号：JPH0659974A

公开(公告)日：1994-03-04

申请号：JP17539892

申请日：1992-07-02

Applicant: IBM

Inventor： OBA NOBUYUKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08

Abstract: PURPOSE: To efficiently execute cache consistency processing to be executed when an access occurs to a main memory from an input/output device. CONSTITUTION: A computer system consists of a processor 1, the cache memory 2 of this processor 1, a main memory 4, the input/output device 6 directly accessible to this main memory, an input/output controller 7, etc., so that the controller 7 may execute the processing of holding the coincidence of data between the cache memory 2 and the main memory 4 at the time of access to the main memory by the device 6. The controller 7 is provided with an address buffer 9 holding the cache line display of the address of the access of the last time so as not to execute the processing of holding coincidence except for first access, when access to the main memory 4 by the device 6 is consecutively occurs within the same address block.

公开(公告)号：JPH04312160A

公开(公告)日：1992-11-04

申请号：JP8900491

申请日：1991-03-29

Applicant: IBM

Inventor： OBA NOBUYUKI ,  KAWACHIYA KIYOKUNI

IPC: G06F15/173 ,  G06F13/36

Abstract: PURPOSE: To provide a generalized aperiodic message transmission system by making each processor generate a response signal to a message passing request signal from another processor, counting response signals, and sending a message to processors as many as the counted value. CONSTITUTION: A DCR 5 specifies the address of the message and when message transmission is successful, the contents of an MDR 6 flow to a message data bus 1b and reaches the destination processor. An LNR 7 specifies whether or not a minimum number of processors are ready to receive the message and an HNR 8 determines whether or not the message can be sent to a maximum number of processors. A parallel counter 9 counts how many processors return affirmative responses and a parallel comparator 10 compares the contents of the parallel counter 9 with the contents of the LNR 7 and selects processors as many as the number of the LNR 8 when affirmative responses are returned from more processors than the value set in the LNR 7, thereby setting them to the DCR 5.

公开(公告)号：JPH01279354A

公开(公告)日：1989-11-09

申请号：JP10447188

申请日：1988-04-28

Applicant: IBM

Inventor： OBA NOBUYUKI

IPC: G06F13/26 ,  G06F13/362 ,  G06F13/374

Abstract: PURPOSE: To perform priority control by a fixed priority system, a progressive system and the mixed system with simple constitution by providing the highest priority register and the lowest priority register in respective bus masters. CONSTITUTION: The value of the lowest priority register 7 of the request priority decision circuit 5 of the bus master is set to a request priority counter 8 first. Then, the value of the counter 8 is counted down for one at the point of time when one of the bus masters starts using a bus. In the meantime, the contents of the counter 8 are supplied to an arbitration bus 3 and a comparator 9 and compared with the contents of the highest priority register 6. Then, when they match, a bus using plate is acquired and the contents of the register 7 are set to the counter 8 again. Thus, by arbitrarily setting the contents of the registers 6 and 7, bus arbitration is performed by various forms.

公开(公告)号：JP2011066629A

公开(公告)日：2011-03-31

申请号：JP2009214679

申请日：2009-09-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBA NOBUYUKI ,  KODA YASUTERU ,  KATAYAMA YASUNAO

IPC: H04L27/36 ,  H04L27/18 ,  H04L27/22 ,  H04L27/38

CPC classification number: H03M1/0624 ,  H03M1/0836 ,  H03M1/66

Abstract: PROBLEM TO BE SOLVED: To detect and correct a phase shift between an I data clock and a Q data clock in a DAC or an ADC used for a modulator or a demodulator regarding a quadrature modulator in a high-speed radio communication. SOLUTION: A phase comparison is made by receiving an I data clock 621 and a Q data clock 631 outputted from an I-DAC and a Q-DAC. A phase comparator having a function of outputting a data clock DELAY signal to a Q-DAC 630 is provided. For phase adjustment, the I data clock and the Q data clock are compared by an XOR, the result is sampled by another phase clock asynchronous with the data clock, and the frequency of a sampling value=0 and the frequency of a sampling value=1 are respectively counted to determine a phase shift of the data clocks from the counts. A delay device 680 to be placed within the DAC or an FPGA is further provided, and a 90-degree shift and a 270-degree shift are discriminated by using a delay function of the data clock. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：检测和校正在用于高速无线电通信中的关于正交调制器的调制器或解调器的DAC或ADC中的I数据时钟和Q数据时钟之间的相移。 解决方案：通过接收从I-DAC和Q-DAC输出的I数据时钟621和Q数据时钟631进行相位比较。 提供了具有向Q-DAC 630输出数据时钟DELAY信号的功能的相位比较器。 对于相位调整，I数据时钟和Q数据时钟通过XOR进行比较，结果由与数据时钟异步的另一个相位时钟进行采样，采样值的频率= 0，采样值的频率= 分别计数1以从计数确定数据时钟的相移。 进一步提供放置在DAC或FPGA内的延迟装置680，并通过使用数据时钟的延迟功能来鉴别90度移位和270度移位。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010128730A

公开(公告)日：2010-06-10

申请号：JP2008301875

申请日：2008-11-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKANO KOJI ,  OBA NOBUYUKI ,  NAKADA TAKEO

IPC: G06F13/38

Abstract: PROBLEM TO BE SOLVED: To provide a device etc. capable of efficiently performing data transfer when transferring measurement data to be observed to a subsequent stage so that a fatal loss of measurement information is prevented even if the measurement data exceeds a transfer band. SOLUTION: The device includes: (A) a data receiver unit for successively receiving occurrence event information and for generating time information including an absolute elapsed time from the start of measurement; (B) a buffer for tentatively storing successive event information and time information; a data amount decision unit for deciding a data amount (C1) initially to be in a first stage, (C2) to be in a second stage when the buffer use rate exceeds a first ascending time threshold, and (C3) in the case of the second stage, to have returned to the first stage when the use rate falls below a first descending time threshold smaller than the first ascending time threshold; and a data transfer unit (D1) in the case of the first stage, for transferring the event information and the time information from the buffer to the subsequent stage intact, and (D2) in the case of the second stage, for transferring the event information from the buffer and coarse time information, having degraded accuracy of the time information, successively to the subsequent stage. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够在将待观察的测量数据传送到后续阶段时能够有效地执行数据传输的装置等，使得即使测量数据超过传送带，也可以防止测量信息的致命丢失 。 该装置包括：（A）数据接收单元，用于连续接收发生事件信息，并用于产生包括从开始测量开始的绝对经过时间的时间信息; （B）暂时存储连续事件信息和时间信息的缓冲器; 数据量判定单元，用于当缓冲器使用率超过第一上升时间阈值时，决定最初处于第一级的数据量（C1），（C2）为第二级，以及（C3）在 第二阶段，当使用率低于小于第一上升时间阈值的第一下降时间阈值时已经返回到第一阶段; 以及在第一阶段的情况下的数据传送单元（D1），用于将事件信息和时间信息从缓冲器传送到后续阶段，并且（D2）在第二阶段的情况下用于传送事件 来自缓冲器的信息和粗略时间信息，具有降低的时间信息的精度，连续到后续阶段。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008225759A

公开(公告)日：2008-09-25

申请号：JP2007061959

申请日：2007-03-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKANO KOJI ,  OBA NOBUYUKI ,  SAKAGUCHI YOSHITAMI

IPC: G06F9/48 ,  G06F11/34

CPC classification number: G06F11/3419

Abstract: PROBLEM TO BE SOLVED: To detect whether or not specific operation is performed in executing a monitored task on an information processor with a simple configuration.
SOLUTION: This detection device has: a cluster storage part storing a range of an execution time belonging to a cluster in association with each the cluster wherein the execution time of the already executed monitored task is classified; an acquisition part acquiring the execution time of the monitored task according to new execution of the monitored task on the information processor; and a decision part deciding that the specific operation is performed in executing the monitored task on condition that the execution time of the newly executed monitored task is not included in the range corresponding to any cluster.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：检测在以简单配置在信息处理器上执行被监视任务是否执行特定操作。 解决方案：该检测装置具有：集群存储部，其存储与已经执行的被监视任务的执行时间分类的每个集群相关联的属于集群的执行时间的范围; 所述获取部根据所述信息处理器的被监视任务的新的执行取得被监视任务的执行时间; 并且判定在执行被监视任务的执行时间不包括在与任何集群对应的范围内的情况下，执行所监视的任务，执行特定操作。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007233521A

公开(公告)日：2007-09-13

申请号：JP2006051843

申请日：2006-02-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKANO KOJI ,  OBA NOBUYUKI

IPC: G06F17/50 ,  G06F11/22

CPC classification number: G01R31/31704

Abstract: PROBLEM TO BE SOLVED: To separate an output signal outputted from an observation object device into transactions. SOLUTION: The observation device for observing operation of the observation object device comprises an output signal acquisition part observing signals outputted from the observation object device and successively acquiring the signal values; a state storage part successively storing the acquired signal values; a determination part determining whether a first signal value newly acquired is identical to a second signal value acquired before the first signal value and stored in the state storage part or not; and a separation part separating and outputting a signal string containing a plurality of signal values acquired between the first signal value and the second signal value as a transaction of output signal, on condition that the first signal value is determined to be identical to the second signal value. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：将从观察对象装置输出的输出信号分离成交易。 观察对象装置观察装置的观察装置包括观察从观察对象装置输出的信号的输出信号取得部，并连续取得信号值。 状态存储部分，其连续地存储所获取的信号值; 确定部件确定新获取的第一信号值是否与在第一信号值之前获取并存储在状态存储部分中的第二信号值相同; 以及分离部分，在第一信号值被确定为与第二信号相同的条件下，分离并输出包含在第一信号值和第二信号值之间获取的多个信号值的信号串作为输出信号的交易 值。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003218872A

公开(公告)日：2003-07-31

申请号：JP2002001328

申请日：2002-01-08

Applicant: IBM

Inventor： TAKAHASHI NOBUAKI ,  NAKADA TAKEO ,  OBA NOBUYUKI

IPC: H04L12/28 ,  H04L1/00 ,  H04L1/24 ,  H04L29/14

Abstract: PROBLEM TO BE SOLVED: To enable a long time observation on a signal traffic on a bus in a measurement object system, and enable real time observation in response to operation of the measurement object system. SOLUTION: The apparatus comprises a bus probe device 10 for extracting bus events occurring on the bus based on the digital bus signals on the bus of the measurement object system, a traffic measuring device 20 for counting the number of times of occurrences of the bus events based on the occurrences information on the extracted bus events, and a console unit 30 for processing by acquiring counted values of the measuring device 20. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH04328665A

公开(公告)日：1992-11-17

申请号：JP11669491

申请日：1991-04-22

Applicant: IBM

Inventor： FUKUDA MUNEHIRO ,  OBA NOBUYUKI ,  NAKADA TAKEO

IPC: G06F9/48 ,  G06F9/50 ,  G06F13/24 ,  G06F13/26 ,  G06F13/362

Abstract: PURPOSE: To distribute I/O interruptions to respective processors by arbitrating the interruptions by using parameters showing the load states of the processors as 1st priority PPR and additionally selecting one processor according to 2nd interruption priority RRPR which varies cyclically unless one processor is not determined. CONSTITUTION: Data of PPR 11 and RRPR 12 are temporarily stored in a buffer 15. The PPR 11 specifies the priority of an I/O interruption corresponding to the execution priority of a process and is used for 1st arbitration based upon the execution priority of the process. The RRPR 12 of each interrupt arbiter is a counter which cyclically counts within the range of the number of the processors and initialized to characteristic priority when the system is actuated to have a different value from any other interrupt arbiter. An encoder sends a selected request signal varying in interruption request level to control logic 14, which is actuated to inhibit an arbitration line 4 to a bus arbiter from being used.