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公开(公告)号:DE10224935A1
公开(公告)日:2002-12-19
申请号:DE10224935
申请日:2002-06-04
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor: MATHAD GANGADHARA S , PANDA SIDDHARTHA , RANADE RAJLV M
IPC: B44C1/22 , C03C25/68 , C23F1/00 , H01L21/00 , H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/762
Abstract: A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.
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公开(公告)号:SG129354A1
公开(公告)日:2007-02-26
申请号:SG200603915
申请日:2006-06-08
Applicant: CHARTERED SEMICONDUCTOR MFG , IBM
Inventor: FU CHONG YUNG , GREENE BRIAN JOSEPH , PANDA SIDDHARTHA , ROVEDO NIVO
Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.
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公开(公告)号:DE10352070A1
公开(公告)日:2004-05-27
申请号:DE10352070
申请日:2003-11-07
Applicant: INFINEON TECHNOLOGIES AG , IBM
Inventor: DOBUZINSKY DAVID , PANDA SIDDHARTHA , WEIS ROLF , WISE RICHARD
IPC: H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/461 , H01L21/68 , H01L21/8242
Abstract: A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon.In such manner, a source of silicon (in the silicon layer) is provided at the wafer edge, such that the silicon loading is improved. In addition, the silicon layer at the wafer edge forms a blocking layer which prevents formation of black silicon.
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公开(公告)号:DE10320944A1
公开(公告)日:2003-11-27
申请号:DE10320944
申请日:2003-05-09
Applicant: INFINEON TECHNOLOGIES AG , IBM
Inventor: MATHAD GANGADHARA , PANDA SIDDHARTHA , RANADE RAJIV
IPC: H01L21/3065 , H01L21/8242
Abstract: A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.
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