公开(公告)号：DE10320944A1

公开(公告)日：2003-11-27

申请号：DE10320944

申请日：2003-05-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MATHAD GANGADHARA ,  PANDA SIDDHARTHA ,  RANADE RAJIV

IPC: H01L21/3065 ,  H01L21/8242

Abstract: A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.

公开(公告)号：DE10328594B4

公开(公告)日：2008-04-24

申请号：DE10328594

申请日：2003-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAIPRAKASH VENKATACHALAN C ,  RANADE RAJIV

IPC: H01L27/108 ,  H01L21/8242

Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：DE69929266D1

公开(公告)日：2006-03-30

申请号：DE69929266

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MICHAELIS ALEXANDER ,  RANADE RAJIV ,  FLIETNER BERTRAND

IPC: H01L21/302 ,  H01L29/94 ,  H01L21/02 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

公开(公告)号：DE10328594A1

公开(公告)日：2004-01-29

申请号：DE10328594

申请日：2003-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PRAIKASH JAI VENKATACHALAN C ,  RANADE RAJIV

IPC: H01L21/8242 ,  H01L27/108

Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：DE69929266T2

公开(公告)日：2006-08-17

申请号：DE69929266

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MICHAELIS ALEXANDER ,  RANADE RAJIV ,  FLIETNER BERTRAND

IPC: H01L21/302 ,  H01L29/94 ,  H01L21/02 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

公开(公告)号：WO0193323A3

公开(公告)日：2002-06-27

申请号：PCT/US0115997

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NAEEM MUNIR D ,  LEE BRIAN S ,  MATHAD GANGADHARA S ,  LEE HEON ,  KIM BYEONG YEOL ,  MORALES ELIZABETH ,  KUDELKA STEPHAN P ,  RANADE RAJIV ,  PARK YOUNG-JIN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311 ,  H01L21/8239

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures

Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， > 30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度

公开(公告)号：WO02073668A2

公开(公告)日：2002-09-19

申请号：PCT/US0208009

申请日：2002-03-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RANADE RAJIV ,  NAEEM MUNIR ,  MATHAD GANGADHARA

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/1087 ,  H01L21/3065 ,  H01L21/3081

Abstract: A method for etching trenches includes providing a patterned mask stack (8) on a substrate (50). A trench is etched in the substrate by forming a tapered-shaped trench portion (60) of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion (61) of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.

Abstract translation: 蚀刻沟槽的方法包括在衬底（50）上提供图案化掩模叠层（8）。 通过形成沟槽的锥形沟槽部分（60），通过采用包括O 2，HBr和NF 3的第一等离子体化学混合物在衬底中的深度变窄来在衬底中蚀刻沟槽。 通过使用包括O 2，HBr和SF 6或F 2的第二等离子体化学混合物，通过蚀刻比衬底中的锥形沟槽部分更深和更宽的第二分布来形成沟槽的延伸部分（61）。