公开(公告)号：CA2068042C

公开(公告)日：1999-03-02

申请号：CA2068042

申请日：1992-05-05

Applicant: IBM

Inventor： LUMELSKY LEON ,  CHOI SUNG M ,  PEEVERS ALAN W ,  PITTAS JOHN L

IPC: G09G5/06 ,  G06T3/00 ,  G06T11/20 ,  G09G5/14 ,  G09G5/36 ,  G09G5/395 ,  H04N5/265 ,  H04N5/272 ,  H04N5/445 ,  H04N7/015

Abstract: Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.

公开(公告)号：CA2067471C

公开(公告)日：1996-10-29

申请号：CA2067471

申请日：1992-04-28

Applicant: IBM

Inventor： PITTAS JOHN LOUIS ,  CHOI SUNG M ,  LUMELSKY LEON ,  PEEVERS ALAN W

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/173 ,  G06T1/00 ,  G06T1/60 ,  G09B5/14 ,  H04L12/40 ,  H04L12/42 ,  H04N1/00 ,  H04N1/46 ,  H04N5/00 ,  H04N7/00 ,  G06F13/38 ,  G06F13/20

Abstract: A high-speed communications network (10) provides singlecast, multicast, or broadcast image data capability and is implemented utilizing the High-Performance Parallel Interface (HPPI) as a physical channel. A server (12) includes both a HPPI receiver and transmitter. Workstations (18) support a HPPI-compatible receiver (14b), but require only a simplified HPPI output port (20). The workstations are connected such the receiver port of each is driven by data and control signals from an upstream server HPPI transmitter port. Handshaking signals, generated by the receiver ports, ripple upstream to the server or to an upstream workstation output port. A packet of data bursts corresponds to either a complete image frame, or to a rectangular subsection thereof, referred to as a window. A first burst is defined to be a Header burst and contains an Image Header that specifies addresses of addressed workstations. Following the Header burst are image data bursts containing pixel data organized in raster format.

公开(公告)号：DE69020279T2

公开(公告)日：1996-02-08

申请号：DE69020279

申请日：1990-08-03

Applicant: IBM

Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

IPC: G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

Abstract: A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

公开(公告)号：DE69020279D1

公开(公告)日：1995-07-27

申请号：DE69020279

申请日：1990-08-03

Applicant: IBM

Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

IPC: G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

Abstract: A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

公开(公告)号：CA2067418A1

公开(公告)日：1993-01-23

申请号：CA2067418

申请日：1992-04-28

Applicant: IBM

Inventor： CHOI SUNG M ,  LUMELSKY LEON ,  PEEVERS ALAN W ,  PITTAS JOHN L

IPC: G06T9/00 ,  G09G5/02 ,  G09G5/04 ,  G09G5/36 ,  H04N1/41 ,  G09G5/22

Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules (34). The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.