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    4.
    发明专利
    未知

    公开(公告)号：DE69225538T2

    公开(公告)日：1999-02-04

    申请号：DE69225538

    申请日：1992-07-03

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G09G5/00 ,  G06F12/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  H04N7/01

    Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.

    5.
    发明专利
    未知

    公开(公告)号：DE69211447T2

    公开(公告)日：1996-12-05

    申请号：DE69211447

    申请日：1992-07-02

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G06T9/00 ,  G09G5/02 ,  G09G5/04 ,  G09G5/36 ,  H04N1/41 ,  G09G5/06

    Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules (34). The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.

    6.
    发明专利
    未知

    公开(公告)号：DE69222247T2

    公开(公告)日：1998-03-26

    申请号：DE69222247

    申请日：1992-07-16

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS ,  SWART CALVIN BRUCE

    IPC: H04N5/202 ,  G06T5/00 ,  G09G1/28 ,  G09G5/04 ,  G09G5/39

    Abstract: An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.

    Multi-source image real time mixing and anti-aliasing
    7.
    发明专利
    Multi-source image real time mixing and anti-aliasing 未知

    公开(公告)号：SG43717A1

    公开(公告)日：1997-11-14

    申请号：SG1996000134

    申请日：1992-07-02

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G09G5/06 ,  G06T3/00 ,  G06T11/20 ,  G09G5/14 ,  G09G5/36 ,  G09G5/395 ,  H04N5/265 ,  H04N5/272 ,  H04N5/262 ,  G09G1/16

    Abstract: Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.

    8.
    发明专利
    未知

    公开(公告)号：DE69222247D1

    公开(公告)日：1997-10-23

    申请号：DE69222247

    申请日：1992-07-16

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS ,  SWART CALVIN BRUCE

    IPC: H04N5/202 ,  G06T5/00 ,  G09G1/28 ,  G09G5/04 ,  G09G5/39

    Abstract: An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.

    10.
    发明专利
    未知

    公开(公告)号：DE69225538D1

    公开(公告)日：1998-06-25

    申请号：DE69225538

    申请日：1992-07-03

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G09G5/00 ,  G06F12/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  H04N7/01

    Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.

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