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    3.
    发明专利
    未知

    公开(公告)号：DE69020279T2

    公开(公告)日：1996-02-08

    申请号：DE69020279

    申请日：1990-08-03

    Applicant: IBM

    Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

    IPC: G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

    Abstract: A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

    4.
    发明专利
    未知

    公开(公告)号：DE69020279D1

    公开(公告)日：1995-07-27

    申请号：DE69020279

    申请日：1990-08-03

    Applicant: IBM

    Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

    IPC: G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

    Abstract: A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

    5.
    发明专利
    未知

    公开(公告)号：DE69222247D1

    公开(公告)日：1997-10-23

    申请号：DE69222247

    申请日：1992-07-16

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS ,  SWART CALVIN BRUCE

    IPC: H04N5/202 ,  G06T5/00 ,  G09G1/28 ,  G09G5/04 ,  G09G5/39

    Abstract: An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.

    7.
    发明专利
    未知

    公开(公告)号：DE69222247T2

    公开(公告)日：1998-03-26

    申请号：DE69222247

    申请日：1992-07-16

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS ,  SWART CALVIN BRUCE

    IPC: H04N5/202 ,  G06T5/00 ,  G09G1/28 ,  G09G5/04 ,  G09G5/39

    Abstract: An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.

    Multi-source image real time mixing and anti-aliasing
    8.
    发明专利
    Multi-source image real time mixing and anti-aliasing 未知

    公开(公告)号：SG43717A1

    公开(公告)日：1997-11-14

    申请号：SG1996000134

    申请日：1992-07-02

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G09G5/06 ,  G06T3/00 ,  G06T11/20 ,  G09G5/14 ,  G09G5/36 ,  G09G5/395 ,  H04N5/265 ,  H04N5/272 ,  H04N5/262 ,  G09G1/16

    Abstract: Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.

    9.
    发明专利
    未知

    公开(公告)号：DE69015536T2

    公开(公告)日：1995-07-06

    申请号：DE69015536

    申请日：1990-06-05

    Applicant: IBM

    Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

    IPC: H04N5/66 ,  G06T3/40 ,  G09G5/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  H04N1/393 ,  H04N5/262 ,  H04N7/01 ,  H04N3/22 ,  G06T3/60 ,  G09G1/00

    Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the controi signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means. In the simplest form of the invention the additional circuitry required comprises only two registers for holding the generated expansion patterns in the horizontal and vertical direction and two shift registers for receiving these patterns and processing same to alter the frame buffer clocks to achieve replication of predetermined lines and pixels as determined from the said expansion pattern.

    10.
    发明专利
    未知

    公开(公告)号：DE69225538D1

    公开(公告)日：1998-06-25

    申请号：DE69225538

    申请日：1992-07-03

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G09G5/00 ,  G06F12/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  H04N7/01

    Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.

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