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1.发明专利
公开(公告)号：PL169117B1
公开(公告)日：1996-06-28
申请号：PL30207692
申请日：1992-06-15
Applicant: IBM
Inventor： CHOI SUNG M , LUMELSKY LEON , PEEVERS ALAN W , PITTAS JOHN LOUIS
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公开(公告)号：DE69015536T2
公开(公告)日：1995-07-06
申请号：DE69015536
申请日：1990-06-05
Applicant: IBM
Inventor： LUMELSKY LEON , PEEVERS ALAN W , CHOI SUNG MIN
IPC: H04N5/66 , G06T3/40 , G09G5/00 , G09G5/02 , G09G5/14 , G09G5/36 , H04N1/393 , H04N5/262 , H04N7/01 , H04N3/22 , G06T3/60 , G09G1/00
Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the controi signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means. In the simplest form of the invention the additional circuitry required comprises only two registers for holding the generated expansion patterns in the horizontal and vertical direction and two shift registers for receiving these patterns and processing same to alter the frame buffer clocks to achieve replication of predetermined lines and pixels as determined from the said expansion pattern.
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公开(公告)号：CA2068042A1
公开(公告)日：1993-01-23
申请号：CA2068042
申请日：1992-05-05
Applicant: IBM
Inventor： LUMELSKY LEON , CHOI SUNG M , PEEVERS ALAN W , PITTAS JOHN L
IPC: G09G5/06 , G06T3/00 , G06T11/20 , G09G5/14 , G09G5/36 , G09G5/395 , H04N5/265 , H04N5/272 , H04N5/445
Abstract: Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.
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公开(公告)号：CA2067418C
公开(公告)日：1998-05-19
申请号：CA2067418
申请日：1992-04-28
Applicant: IBM
Inventor： PITTAS JOHN L , PEEVERS ALAN W , LUMELSKY LEON , CHOI SUNG M
Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules. The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.
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公开(公告)号：CA2000021C
公开(公告)日：1994-11-08
申请号：CA2000021
申请日：1989-10-02
Applicant: IBM
Inventor： LUMELSKY LEON , PEEVERS ALAN W
Abstract: YO989-010 A method and apparatus for synchronizing two independent rasters, such that a standard TV video and a high resolution computer generated graphics video may each be displayed on a high resolution graphics monitor. This is accomplished utilizing dual frame buffers. A TV frame buffer, comprises a dual port VRAM, with the serial and random ports operating asynchronously. The primary port receives incoming TV video synchronously as it comes in, and the secondary port reads the TV video out synchronously with the high resolution graphics monitor. A high resolution frame buffer in a computer is utilized to store high resolution graphics which is read out synchronously with the high resolution graphics monitor. A switching mechanism selects which of the TV video and the high resolution graphics video is to be displayed at a given time. The TV frame buffer includes an on screen and off screen portion. The computer provides computer data, including high resolution graphics data and audio data to the TV frame buffer, with the graphics data being stored in the on screen portion and the audio data being stored in the off screen portion. The audio data is read out to an audio circuit for replay. The graphics data is combined with the TV video for purposes of windowing.
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Patent Agency Ranking
公开(公告)号：CA2067471A1
公开(公告)日：1993-01-23
申请号：CA2067471
申请日：1992-04-28
Applicant: IBM
Inventor： CHOI SUNG M , LUMELSKY LEON , PEEVERS ALAN W , PITTAS JOHN L
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公开(公告)号：CA2068001C
公开(公告)日：1999-03-02
申请号：CA2068001
申请日：1992-05-05
Applicant: IBM
Inventor： LUMELSKY LEON , CHOI SUNG M , PEEVERS ALAN W , PITTAS JOHN L
IPC: G09G5/00 , G06F12/00 , G09G5/02 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/395 , H04N7/01 , G09G1/16
Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.
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公开(公告)号：DE69015536D1
公开(公告)日：1995-02-09
申请号：DE69015536
申请日：1990-06-05
Applicant: IBM
Inventor： LUMELSKY LEON , PEEVERS ALAN W , CHOI SUNG MIN
IPC: H04N5/66 , G06T3/40 , G09G5/00 , G09G5/02 , G09G5/14 , G09G5/36 , H04N1/393 , H04N5/262 , H04N7/01 , H04N3/22 , G06T3/60 , G09G1/00
Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the controi signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means. In the simplest form of the invention the additional circuitry required comprises only two registers for holding the generated expansion patterns in the horizontal and vertical direction and two shift registers for receiving these patterns and processing same to alter the frame buffer clocks to achieve replication of predetermined lines and pixels as determined from the said expansion pattern.
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公开(公告)号：CA1313415C
公开(公告)日：1993-02-02
申请号：CA589106
申请日：1989-01-25
Applicant: IBM
Inventor： GUPTA SATISH , LARKY STEVEN P , PEEVERS ALAN W , ST CLAIR JOE C
IPC: G09G1/02 , G06F3/153 , G06F12/08 , G06F12/10 , G09G5/00 , G09G5/14 , G09G5/36 , G09G5/39 , G09G1/16
Abstract: Y0988-006 A display control means such as a virtual display adapter allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory. This large area of memory includes system memory, and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.
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公开(公告)号：CA2068001A1
公开(公告)日：1993-01-23
申请号：CA2068001
申请日：1992-05-05
Applicant: IBM
Inventor： LUMELSKY LEON , CHOI SUNG M , PEEVERS ALAN W , PITTAS JOHN L
IPC: G09G5/00 , G06F12/00 , G09G5/02 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/395 , H04N7/01 , G09G1/16
Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.
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