12.
    发明专利
    未知

    公开(公告)号:DE3586635D1

    公开(公告)日:1992-10-22

    申请号:DE3586635

    申请日:1985-02-28

    Applicant: IBM

    Abstract: An efficient prefetching mechanism is disclosed for a system comprising a cache. In addition to the normal cache directory (11), a two-level shadow directory (13, 15) is provided. When an information block is accessed, a parent identifer (P) derived from the block address is stored in the top level (13) of the shadow directory. The address of a subsequently accessed block (Q) is stored in the second level (15) of the shadow directory, in a position associated with the first-level position of the respective parent identifier. … With each access to an information block, a check is made whether the respective parent identifier (P) is already stored in the first level of the shadow directory. If it is found, then the descendant address (Q) from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids with high probability the occurence of cache misses.

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