公开(公告)号：JP2005019994A

公开(公告)日：2005-01-20

申请号：JP2004183609

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDORA DEIVAKARUNI

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/3215 ,  H01L27/1087

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a buried plate in a trench capacitor, thereby overcoming limitation in the conventional method.
SOLUTION: A dopant source material such as ASG is completely filled into a trench. Next, a recess is formed on this dopant source material, and a collar material is deposited thereon. Thus, a collar is formed on the upper side portion of the trench. After the buried plate is formed through drive-in of the dopant, the dopant source material is removed and the collar material may be removed.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在沟槽电容器中形成掩埋板的方法，从而克服了常规方法中的限制。 解决方案：诸如ASG的掺杂剂源材料被完全填充到沟槽中。 接下来，在该掺杂剂源材料上形成凹部，并且在其上沉积套环材料。 因此，在沟槽的上侧部分上形成有套环。 在通过掺杂剂的驱入形成掩埋板之后，去除掺杂剂源材料并且可以去除套环材料。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002270700A

公开(公告)日：2002-09-20

申请号：JP2002002654

申请日：2002-01-09

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NESBIT LARRY A ,  FALTERMEIER JOHNATHAN E ,  RAMACHANDORA DEIVAKARUNI ,  BERGNER WOLFGANG

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a bit-line contact and formation method thereof for a vertical DRAM array, using a bit-line contact mask. SOLUTION: In this method, a gate conductor line is formed. An oxide layer 35 is adhered to the gate conductor line, and a bit-line contact mask 40 is formed on a part of the oxide layer 35. The bit-line contact mask 40 is etched, and a silicon layer 45 is made to stick on a substrate 5. A bit-line layer 50 is adhered to the silicon layer 45. Masking and etching processes are carried out with a bit-line layer 50. An M0 metal 60 is made to adhere to the silicon layer 45, as well as on both sides of non-etching part of the bit-line (M0) layer 50, and forms the left and right bit lines.