公开(公告)号：JP2002270700A

公开(公告)日：2002-09-20

申请号：JP2002002654

申请日：2002-01-09

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NESBIT LARRY A ,  FALTERMEIER JOHNATHAN E ,  RAMACHANDORA DEIVAKARUNI ,  BERGNER WOLFGANG

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a bit-line contact and formation method thereof for a vertical DRAM array, using a bit-line contact mask. SOLUTION: In this method, a gate conductor line is formed. An oxide layer 35 is adhered to the gate conductor line, and a bit-line contact mask 40 is formed on a part of the oxide layer 35. The bit-line contact mask 40 is etched, and a silicon layer 45 is made to stick on a substrate 5. A bit-line layer 50 is adhered to the silicon layer 45. Masking and etching processes are carried out with a bit-line layer 50. An M0 metal 60 is made to adhere to the silicon layer 45, as well as on both sides of non-etching part of the bit-line (M0) layer 50, and forms the left and right bit lines.

公开(公告)号：WO0141201A9

公开(公告)日：2002-05-30

申请号：PCT/US0032471

申请日：2000-11-27

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： FALTERMEIER JOHNATHAN E ,  GRUENING ULRIKE ,  HEGDE SURYANARAYAN ,  JAMMY RAJARAO ,  LEE BRIAN S ,  TEWS HELMUT

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/12 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  Y10S438/931

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a (100) crystal plane and a (110) crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the (110) crystal plane of the trench side wall, but not into the (100) crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Abstract translation: 一种用于制造垂直晶体管的栅极氧化物的工艺。 在第一步骤中，在衬底中形成沟槽，沟槽从衬底的顶表面延伸并且具有沟槽底部和沟槽侧壁。 沟槽侧壁包括（100）晶面和（110）晶面。 接下来，在沟槽侧壁上形成均匀厚度的牺牲层。 在形成牺牲层之后，通过牺牲层注入氮离子，使得氮离子注入到沟槽侧壁的（110）晶面中，但不注入沟槽侧壁的（100）晶面。 然后去除牺牲层，并且沟槽侧壁被氧化以形成栅极氧化物。

公开(公告)号：DE102004016705B4

公开(公告)日：2008-04-17

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/283 ,  H01L21/311 ,  H01L21/60 ,  H01L21/8239 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/768

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：DE102004016705A1

公开(公告)日：2004-11-25

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.