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    BIT-LINE CONTACT AND FORMING METHOD THEREFOR
    1.
    发明专利
    BIT-LINE CONTACT AND FORMING METHOD THEREFOR 审中-公开

    公开(公告)号：JP2002270700A

    公开(公告)日：2002-09-20

    申请号：JP2002002654

    申请日：2002-01-09

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： NESBIT LARRY A ,  FALTERMEIER JOHNATHAN E ,  RAMACHANDORA DEIVAKARUNI ,  BERGNER WOLFGANG

    IPC: H01L21/768 ,  H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a bit-line contact and formation method thereof for a vertical DRAM array, using a bit-line contact mask. SOLUTION: In this method, a gate conductor line is formed. An oxide layer 35 is adhered to the gate conductor line, and a bit-line contact mask 40 is formed on a part of the oxide layer 35. The bit-line contact mask 40 is etched, and a silicon layer 45 is made to stick on a substrate 5. A bit-line layer 50 is adhered to the silicon layer 45. Masking and etching processes are carried out with a bit-line layer 50. An M0 metal 60 is made to adhere to the silicon layer 45, as well as on both sides of non-etching part of the bit-line (M0) layer 50, and forms the left and right bit lines.

    ADJUSTMENT OF THRESHOLD VOLTAGE AT CORNER OF MOSFET DEVICE
    2.
    发明专利
    ADJUSTMENT OF THRESHOLD VOLTAGE AT CORNER OF MOSFET DEVICE 失效

    公开(公告)号：JPH10214965A

    公开(公告)日：1998-08-11

    申请号：JP855498

    申请日：1998-01-20

    Applicant: IBM

    Inventor： GAMBINO JEFFREY P ,  GARRY BELLA BRONNER ,  MANDELMAN JACK ALLAN ,  NESBIT LARRY A

    IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234

    Abstract: PROBLEM TO BE SOLVED: To adjust the threshold voltage at the corner of a device without requiring any additional mask by doping the central part of a channel region at some concentration and doping a channel region adjacent to a corner region at a higher concentration. SOLUTION: N type (arsenic) dopant ions 19 are implanted compensatingly. The compensatory implantation is performed in order to compensate for the threshold voltage implantation at the part of the side wall of STI trench structures 18a-18c contiguous to the corner of a substrate 12 other than the corner region 25 and to suppress the effect of P-type ion implantation 21 in the channel region onto the following stage by means of N type doping ions 19 so that the corner region 25 has a higher doping concentration after boron B doping stage. A spacer 16 prevents the compensatory implantation at the corner of the device except the central channel regions 20a, 20b, 20c and 20d.

    CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS
    3.
    发明申请
    CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS 审中-公开
    用于沟槽电容器的碳纳米管导体

    公开(公告)号：WO2005069372A8

    公开(公告)日：2005-11-03

    申请号：PCT/US0340295

    申请日：2003-12-18

    Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

    Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

    Abstract translation: 沟槽型存储器件包括在衬底（100）中的沟槽，衬有沟槽的碳纳米管束（202）和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成沟槽衬里的开放柱状结构。 该装置通过在基底上提供碳纳米管催化剂结构并在基底中图案化沟槽而形成; 然后将碳纳米管向下生长到沟槽中以将沟槽与碳纳米管束对齐，之后用沟槽导体填充沟槽。

    METHOD FOR SIMULTANEOUSLY FORMING LINE INTERCONNECTION AND BORDERLESS CONTACT TO DIFFUSED PART
    4.
    发明专利
    METHOD FOR SIMULTANEOUSLY FORMING LINE INTERCONNECTION AND BORDERLESS CONTACT TO DIFFUSED PART 失效

    公开(公告)号：JP2001223271A

    公开(公告)日：2001-08-17

    申请号：JP2001002760

    申请日：2001-01-10

    Applicant: IBM

    Inventor： DIVAKARUNI RAMA ,  NESBIT LARRY A ,  RADENS CARL J

    IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To simultaneously form a line interconnection of a bit line or the like and borderless contact to a diffused part such as bit line contact. SOLUTION: A semiconductor substrate contains a previously patterned gate stack 12 on the substrate, is covered with a first dielectric substance 40 for forming a first level 42 and then deposited with a second dielectric substance 44 to form a second level 46. A line interconnection opening 62 is formed at a second level 46 by a lithography and etching. The etching is continued to a microcrystallized region of an array region 30 of the substrate, and formed with a borderless contact opening between the gate stacks 12 corresponding to the line interconnection such as an opening of the bit line or the like. These openings are filled with one or more conductors to form the contact with the diffused part such as bit line contact or the like corresponding to the line interconnection of the bit line or the like.

    METHOD OF FORMING DUAL-DAMASCENE INTERCONNECTION AND STRUCTURE USING THE METHOD
    9.
    发明专利
    METHOD OF FORMING DUAL-DAMASCENE INTERCONNECTION AND STRUCTURE USING THE METHOD 审中-公开

    公开(公告)号：JP2002289691A

    公开(公告)日：2002-10-04

    申请号：JP2002021019

    申请日：2002-01-30

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  NESBIT LARRY A

    IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide a structure and method of forming a dual-damascene structure. SOLUTION: The method (and structure) of forming interconnection on a semiconductor substrate includes a step for forming a relatively narrow first structure in a dielectric material formed on the semiconductor substrate, a step for forming a relatively wide second structure in the dielectric material formed on the semiconductor substrate, a step for forming a liner in the first and second structure so that the first structure is substantially filled with the liner and the second structure is not substantially filled, with the liner and a step for metallizing the liner to completely fill the second structure.

    METHOD OF PRODUCING A THIN SILICON-ON-INSULATOR LAYER
    10.
    发明专利
    METHOD OF PRODUCING A THIN SILICON-ON-INSULATOR LAYER 未知

    公开(公告)号：CA1218762A

    公开(公告)日：1987-03-03

    申请号：CA495661

    申请日：1985-11-19

    Applicant: IBM

    Inventor： ABERNATHEY JOHN R ,  LASKY JEROME B ,  NESBIT LARRY A ,  SEDGWICK THOMAS O ,  STIFFLER SCOTT R

    IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/306

    Abstract: A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness. BU9-84-031

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