公开(公告)号：JPH08235793A

公开(公告)日：1996-09-13

申请号：JP32736395

申请日：1995-12-15

Applicant: IBM

Inventor： YAMAGUCHI MARIO ,  HASHIMOTO MINORU ,  SAKAI TATSUYA ,  JIYON HAZUUERU

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/10

Abstract: PROBLEM TO BE SOLVED: To improve the reliability by discriminating an error in correspondence between data held on a disk and addresses, and then store more information on the disk. SOLUTION: User data D when written is held in a register 46, and an error correction code ECC is generated by ECC generation algorithm Ar from both the user data D and its sector information (ID). The record consisting of the user data D and generated ECC is written on the disk; when the record is read out, the user data Dr of the read record Rr is. held temporarily in the register 46, the ECC is separated from the read record Rr, and an error check on the combined data of the user data D and sector information used as the address is made by ECC check algorithm. Only when it is judged by this error check that the sector information contains no error, the user data held in the register 46 is corrected and outputted to a host.

公开(公告)号：JP2008226280A

公开(公告)日：2008-09-25

申请号：JP2008166411

申请日：2008-06-25

Applicant: Internatl Business Mach Corp ,  Renesas Technology Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ルネサステクノロジ

Inventor： UEKI HIROSHI ,  ITO SAKAE ,  SAKAI TATSUYA ,  MURAKAMI MASAYUKI

IPC: G06F12/06

Abstract: PROBLEM TO BE SOLVED: To obtain a system LSI for enabling a control LSI to read data from a memory of an MPU at a high speed.
SOLUTION: When a control circuit outputs an address and a read access request signal, the address is decoded, when the address is an address within an area of the memory, the address and the read access request signal are outputted to a data interface circuit, and an access circuit for acquiring data from the data interface circuit is incorporated in the control LSI.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：获得用于使控制LSI能够高速地从MPU的存储器读取数据的系统LSI。 解决方案：当控制电路输出地址和读取访问请求信号时，地址被解码，当地址是存储器区域内的地址时，地址和读取访问请求信号被输出到数据 接口电路和用于从数据接口电路获取数据的访问电路并入控制LSI中。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JPH10269676A

公开(公告)日：1998-10-09

申请号：JP6879197

申请日：1997-03-21

Applicant: MITSUBISHI ELECTRIC CORP ,  IBM

Inventor： ITO SAKAE ,  SAKAI TATSUYA ,  MURAKAMI MASAYUKI ,  NUMATA TSUTOMU

IPC: G11B19/00 ,  G06F3/06 ,  G11B19/02

Abstract: PROBLEM TO BE SOLVED: To accelerate an input/output of the data by continuously, discretely or continuous/concrete mixedly performing plural times of data inputs/outputs with a hard disk controller by a once access request command imparted from a CPU at an optional access time at every time according to a response status generated from a control resource access condition. SOLUTION: The timing outputting a response status signal (ACK) is decided by a processing state of a hard disk controller(HDC) 34, and the matter that an access time of a microcomputer unit(MCU) 33 is extended is possible. Since the MCU 33 is clock synchronized with the HDC 34, the resource accessible in a short time such as a register on the HDC 34 is transferred in a short time without a delay of the ACK. In the case of continuous access, though a head address of an access request signal is outputted from the MCU 33, a succeeding address is generated by an addition circuit in the HDC 34.

公开(公告)号：JP2000155751A

公开(公告)日：2000-06-06

申请号：JP32832898

申请日：1998-11-18

Applicant: MITSUBISHI ELECTRIC CORP ,  IBM

Inventor： UEKI HIROSHI ,  ITO SAKAE ,  SAKAI TATSUYA ,  MURAKAMI MASAYUKI

IPC: G06F9/32 ,  G06F3/06 ,  G06F9/38 ,  G06F12/00 ,  G06F13/28 ,  G06F15/78 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To enable CPU of an MPU to read a program code out of the memory of a control LSI fast by incorporating in the control LSI a code interface circuit which supplies the program code stored in the memory to the CPU. SOLUTION: The CPU 3 of the MPU 1 outputs a branch request signal RCLR and a branch address AD-CPU to both CIU 4 and CIU 21 at a program address branch time. The CIU 4 and CIU 21 once receiving the branch address AD-CPU decode the branch address AD-CPU and decide whether the address is in address ranges assigned to themselves. The CIU 21 outputs the value of the branch address AD-CPU to the address bus of HDC 2 when the value of the branch address AD-CPU is in its address range. The CIU 21 supplies the program code to the CPU 3 independently of 'code prefetching operation'.

公开(公告)号：JP2000137939A

公开(公告)日：2000-05-16

申请号：JP30821898

申请日：1998-10-29

Applicant: IBM

Inventor： SAKAI TATSUYA ,  TOKIZONO AKIRA ,  KAGAMI NAOYUKI ,  KURODA TAKASHI

IPC: G11B21/08 ,  G11B5/596 ,  G11B19/28 ,  G11B21/10 ,  G11B27/30 ,  G11B19/02 ,  G11B19/247

Abstract: PROBLEM TO BE SOLVED: To provide a disk drive device, a servo controller and a control device, which are capable of contributing to the improvement of performance of the disk drive device. SOLUTION: When data for showing the reproduction level of a servo pattern are supplied from a channel 5 through a servo control part 21, the calculation for the servo control is executed by an SA(servo assist) 23 independently of an MPU 12 and the calculated result is supplied to a VCM(voice coil motor) driving part 6 through a SIO(serial I/O) 22 to drive a head arm 3. The selection is made by an interruption generating part 26 with regard to whether the interruption against the MPU 12 is generated for every reproduction of the servo pattern or the interruption against the MPU 12 is generated based on condition signals from the SC(servo control part) 21, SA 23 and DC(drive control part) 25, according to the selection from the SA 23 or MPU 12.

公开(公告)号：JPH1166695A

公开(公告)日：1999-03-09

申请号：JP21864197

申请日：1997-08-13

Applicant: IBM

Inventor： SAKAI TATSUYA ,  MURAKAMI MASAYUKI ,  KAGAMI NAOYUKI ,  NAKAGAWA YUZO

IPC: G11B21/10 ,  G11B5/596 ,  G11B19/02

Abstract: PROBLEM TO BE SOLVED: To reduce a processing load of an MPU without increasing costs so much and to easily realize an advanced servo control. SOLUTION: Reproduced levels A, B, C and D of respective burst patterns from a channel 5 is subject to an AD conversion by ADC(A/D converter) 16 and are set to an ADC REG(ADC register) 17. A parameter such as a position error of a head 2 is obtained, independent on an MPU 12, by an SA 23 in accordance with the reproduced levels of the respective burst patterns held in the ADC REG 17 and instructions from the MPU 12, etc., held in an SRAM 24, survo data (DACOUT) for driving a VCM(voice.coil.motor) are computed in accordance therewith and are supplied to a DAC of a VCM driving part 6 via an SIO 22.

公开(公告)号：JPH06214934A

公开(公告)日：1994-08-05

申请号：JP30835392

申请日：1992-11-18

Applicant: IBM

Inventor： KIGAMI YUJI ,  NUMATA TSUTOMU ,  SAKAI TATSUYA ,  SHIMIZU KENJI

IPC: G06F3/06 ,  G06F9/445 ,  G06F13/12 ,  G06F13/38

Abstract: PURPOSE: To provide a programmable storage controller which can minimize the intervention of a microprocessor and also excels in both extendibility and flexibility. CONSTITUTION: This controller includes a buffer 16 which stores a data transfer control program in addition to the data that are transferred between a host 10 and an external storage 14, a controller 18 which reads the data transfer control program out of the buffer 16 and carries it out, and a microprocessor 20 which starts to read the program out of the buffer 16 and to send it to the controller 18 in response to the command given from the host 10. The controller 18 controls the data that are transferred between the host 10 and the storage 14 independently of the microporcessor 20. Meanwhile, the processor 20 can carry out other jobs.