-
公开(公告)号：DE69325774T2
公开(公告)日：2000-03-02
申请号：DE69325774
申请日：1993-11-09
Applicant: IBM
Inventor： NUMATA TSUTOMU , KIGAMI YUJI , SAKAI TATSUYA , SHIMIZU KENJI
Abstract: A programmable external storage control apparatus is provided which requires minimum intervention of a microprocessor and has more extendibility and flexibility. It includes a buffer (16) which stores a data transfer control program in addition to data to be transferred between a host (10) and an external storage (14), a controller (18) which reads from the buffer (16) and executes the data transfer control programs, and a microprocessor (20) which starts reading of the program from the buffer (16) to the controller (18) in response to a command from the host (10). The controller (18) controls data transfer between the host and the external storage independently of the microprocessor (20) while the microprocessor (20) may execute other jobs.
-
公开(公告)号：DE69325774D1
公开(公告)日：1999-09-02
申请号：DE69325774
申请日：1993-11-09
Applicant: IBM
Inventor： NUMATA TSUTOMU , KIGAMI YUJI , SAKAI TATSUYA , SHIMIZU KENJI
Abstract: A programmable external storage control apparatus is provided which requires minimum intervention of a microprocessor and has more extendibility and flexibility. It includes a buffer (16) which stores a data transfer control program in addition to data to be transferred between a host (10) and an external storage (14), a controller (18) which reads from the buffer (16) and executes the data transfer control programs, and a microprocessor (20) which starts reading of the program from the buffer (16) to the controller (18) in response to a command from the host (10). The controller (18) controls data transfer between the host and the external storage independently of the microprocessor (20) while the microprocessor (20) may execute other jobs.
-
公开(公告)号：SG44424A1
公开(公告)日：1997-12-19
申请号：SG1996000329
申请日：1993-11-09
Applicant: IBM
Inventor： NUMATA TSUTOMU , KIGAMI YUJI , SAKAI TATSUYA , SHIMIZU KENJI
Abstract: A programmable external storage control apparatus is provided which requires minimum intervention of a microprocessor and has more extendibility and flexibility. It includes a buffer (16) which stores a data transfer control program in addition to data to be transferred between a host (10) and an external storage (14), a controller (18) which reads from the buffer (16) and executes the data transfer control programs, and a microprocessor (20) which starts reading of the program from the buffer (16) to the controller (18) in response to a command from the host (10). The controller (18) controls data transfer between the host and the external storage independently of the microprocessor (20) while the microprocessor (20) may execute other jobs.
-
公开(公告)号：JP2000137960A
公开(公告)日：2000-05-16
申请号：JP30892398
申请日：1998-10-29
Applicant: IBM
Inventor： KAGAMI NAOYUKI , TOKIZONO AKIRA , MUTUTANBII SURIIJAYANTA , SAKAI TATSUYA , YONEDA ISAO , HIEN FUU DAN , ARN SHARMA
Abstract: PROBLEM TO BE SOLVED: To effectively perform disturbance suppression, mechanical resonance suppression by providing plural filter means and constituting the filter means in multistage with a parallel or serial form for a position control output with instructions of an MPU when an actuator is position controlled. SOLUTION: A servo control part SV 21 receives a signal from a servo pattern of a magnetic disk 1 to process it, and generates a servo signal output DACOUT moving a head arm 3 through a hardware sequencer SA 23 to send it to a voice coil motor VCM drive part 6. The SA 23 consists of plural digital filters, and sets arrangement of respective digital filters for the servo signal output DACOUT based on the instructions from the MPU 40. For instance, peak filters are arranged serially, and a peak is given to an output gain at a required frequency. Or, notch filters are arranged parallel, and the output gain suppressing the mechanical resonance is obtained.
-
公开(公告)号：JP2001282541A
公开(公告)日：2001-10-12
申请号：JP2000089860
申请日：2000-03-28
Applicant: IBM
Inventor： MURAKAMI MASAYUKI , TAKASE YASUHIRO , SAKAI TATSUYA
Abstract: PROBLEM TO BE SOLVED: To easily change a microcode in a control element using a system LSI forming a DRAM in the same chip substrate without generating a production lead time and requiring the reevaluation of the LSI. SOLUTION: A semiconductor device 10 connecting its terminal 17 to an external serial ROM 11 is provided with a DRAM 14 formed on the same chip substrate, a comparator 20 for inputting data of one byte from the terminal 17 and comparing whether the data is 'FF' or '00' (both of which are hexadecimal numbers) or not and a selector 18 for selecting download from an internal serial mask ROM 19 when the compared result is true or selecting download from the external serial ROM 11 when the compared result is false. The downloaded program is recorded in the DRAM 14.
-
Patent Agency Ranking6.发明专利
公开(公告)号：JP2001222474A
公开(公告)日：2001-08-17
申请号：JP2000029103
申请日：2000-02-07
Applicant: IBM
Inventor： OSHIKAWA HIROSHI , SAKAI TATSUYA , ASANO HIDEO , SATO MASAHIKO
IPC: G06F3/00 , G06F13/00 , G06F13/38 , H03K19/0175 , H03K19/0185 , H04L1/00 , H04L25/02
Abstract: PROBLEM TO BE SOLVED: To realize a high signal integrity at all settable data transfer speeds. SOLUTION: A signal output device capable of setting up plural different data transfer speeds and outputting a signal to a signal receiver at a certain set data transfer speed via an ATA cable 2 is provided with a driver circuit 53 capable of setting up plural different through rates and outputting the signal to the ATA cable 2 at a through rate set in accordance with a through rate control signal SRC and a control means for setting up the through rate of the driver circuit 53 in accordance with the set data transfer speed.
-
公开(公告)号：JP2000163872A
公开(公告)日：2000-06-16
申请号：JP33581798
申请日：1998-11-26
Applicant: IBM
Inventor： UEDA TETSUO , FUKUSHIMA YUKIO , SAKAI TATSUYA
Abstract: PROBLEM TO BE SOLVED: To obtain a preventing method for off-track-write of a head by which overkill caused by needless write-inhibition can be reduced, a storage device utilizing it, and a position predicting method using it and a device. SOLUTION: Pn and Vn are obtained from a read out value of a servo pattern of the nth, while the following prospected PESn+1 is obtained based on obtained Pn, Vn, and Un obtained from an output of a servo controller, [prospected PESn+1=Pn+Vn+kUn (where, Pn: PES(position error signal) in a servo pattern (n), Vn: speed (Vn=Pn-P(n-1)) in a servo pattern (n), Un: an output of a servo controller in a servo pattern (n) k: constant)], when each absolute value of obtained Pn, Vn, prospected PESn+1 satisfies any condition of the following conditions (1) to (3), (1)|Pn|>C1, (2)|Vn|>C2 (3)|Predicated PESn+1|>C3 (where, C1, C2, C3: constant), and writing data in a track between the servo pattern of nth by a head and a servo pattern of (n+1)th is inhibited.
-
公开(公告)号：JP2000155701A
公开(公告)日：2000-06-06
申请号：JP32831598
申请日：1998-11-18
Applicant: MITSUBISHI ELECTRIC CORP , MITSUBISHI DENKI SYS LSI DES , IBM
Inventor： KANZAKI TERUAKI , ITO SAKAE , SAKAI TATSUYA , UCHIIKE HIROSHI
Abstract: PROBLEM TO BE SOLVED: To obtain a debugging circuit which can efficiently debug a program. SOLUTION: This debugging circuit 2 accepts a trace event of a functional block A on the condition that a CPU 5 generates no trace event when the functional block A generates the trace event, and obtains trace data from the functional block A in this case in synchronism with the reference clock CLK of the CPU 5 at the time of receiving the trace event of the functional block A.
-
公开(公告)号：JP2000057707A
公开(公告)日：2000-02-25
申请号：JP23081898
申请日：1998-08-17
Applicant: IBM
Inventor： KATO KATSUHIKO , KURODA TAKASHI , SAKAI TATSUYA
Abstract: PROBLEM TO BE SOLVED: To provide a reproduction control apparatus, a reproduction control method and a disk drive device, in which the reliability for data reproduction is enhanced. SOLUTION: When an error contained in reproduced data from maximum likelihood decoding section 24 is equal to or less than the error correction ability of an error correction system 10, data for which the error correction has been performed by holding, in a register 12, an error position and pattern determined by an error calculating section 11 are sequentially output. When an error exceeds the error correction cap ability, the data is re-read, and an output of a byte counter 7, which indicates the position of the reproduced data when a viterbi decoder error signal has been supplied, is supplied to the register 12, and the error correction is performed in accordance with the thus-supplied error position as well as the error pattern determined by the error calculating section 11.
-
公开(公告)号：JPH10214201A
公开(公告)日：1998-08-11
申请号：JP1574397
申请日：1997-01-29
Applicant: MITSUBISHI ELECTRIC CORP , MITSUBISHI DENKI SYS LSI DES , IBM
Inventor： ITO SAKAE , KANZAKI TERUAKI , AKATSUKI TADAYUKI , SAKAI TATSUYA , NUMATA TSUTOMU , NAKAMURA YASUHIRO
Abstract: PROBLEM TO BE SOLVED: To obtain a microcomputer in which a debug circuit equipped with various functions used at the time of program debugging is provided in the microcomputer, and a flash memory electrically capable of writing/erasing incorporated on the same chip can be used as an emulation memory. SOLUTION: This device is provided with a flash memory 6 electrically capable of writing/erasing in which a program in a development stage is stored and a debug circuit 7 having an exclusive input and output terminal 8 for connection with an outside ICE are incorporated in this device. The debug circuit 7 is provided with a communicating function with a CPU 1, a communicating function with the ICE, the trace function of the operating state of the CPU 1, break function for generating debug interruption, function for writing a program code from the ICE in the flash memory 6, and function for transmitting the content of the flash memory 6 to the ICE.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.02 seconds)
