公开(公告)号：JPH09180437A

公开(公告)日：1997-07-11

申请号：JP33365295

申请日：1995-12-21

Applicant: IBM

Inventor： SATO AKASHI ,  KATAYAMA YASUNAO

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To read or write data without any interruption at a constant or short access time regardless of, for example, the timing for reading, writing, or refreshing data in a DRAM. SOLUTION: When a request for reading or writing burst data is continuously inputted, a row decode(RD) and a column decode(CD) by a row decoder 42 and a column decoder 52, an array access(AR) and a recharge(PR) due to a data line driver 24, a bit switch 26, and a sense amplifier 28, and data transfer(TR) due to a write buffer 52 or a read buffer 54 are performed in parallel in pipeline system. When a timing for refreshing a DRAM array 22 arrives, a refresh address which is retained at a refresh controller 40 is outputted while burst data are being transferred and a series of refresh processing consisting of (RD), (AR), and (PR) are performed.

公开(公告)号：JPH08242176A

公开(公告)日：1996-09-17

申请号：JP21385295

申请日：1995-08-22

Applicant: IBM

Inventor： SATO AKASHI

IPC: H03M7/46 ,  G06F17/30 ,  H03M7/30

Abstract: PROBLEM TO BE SOLVED: To accelerate data compression by feeding back a signal outputted from an OR circuit to a signal generation circuit as a signal ORFB through a latch circuit and another OR circuit. SOLUTION: Characters to be retrieved are successively inputted to a write buffer 56 and respective cell strings in a CAM compare these characters with their stored character data and output respective compared results to a compared result control circuit 80 through a match line MATCH. The compared results are successively stored in latches 82, 84. When an inputted signal ORFB is low, each signal generation circuit 86 outputs an AND result between the output of the latch 82 and the output of a prestage latch 88 to a priority encoder 74 and an OR circuit 90 through the latch 88, and when the signal ORFB is high, the circuit outputs an AND result between the output of the latch 82 and the output of the prestage latch 84. Encoders 74, 76 respectively output the OR results of respective input signals as coincident signals MSIG0, MSIG representing compared results. A signal outputted from an OR circuit 90 is inputted to respective signal generation circuit 86 as a signal ORFB through a latch 92 and an OR circuit 94. Since the length of a path allowing a signal to pass is shortened to a half by one period of a clock, data compression can be accelerated.

公开(公告)号：JPH06131266A

公开(公告)日：1994-05-13

申请号：JP25628492

申请日：1992-09-25

Applicant: IBM

Inventor： NIIJIMA HIDETO ,  SATO AKASHI ,  SAKAGAMI YOSHIKATSU

IPC: G06F12/08 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/10 ,  G06F12/12

Abstract: PURPOSE: To execute a program without reading it on a main memory unit and to unitarily manage the program and data on a randomly accessible and rewritable memory without distinguishing them. CONSTITUTION: A computer system is provided with a CPU for converting addresses by referring to a real/virtual address conversion table provided with a page table 25 and an external storage device for using the randomly accessible and rewritable memory connected to the CPU. The page table 25 is constituted so as to make the codes of the program be continuous on the virtual address space of the CPU corresponding to an execution order, and by referring to the real/virtual address conversion table provided with the page table, the program stored in the external storage device is read from the external storage device and executed by using a virtual address. Also, the real address of the CPU is allocated only to the data area of the randomly accessible memory.