公开(公告)号：GB2490819B

公开(公告)日：2014-03-26

申请号：GB201213193

申请日：2011-02-24

Applicant: IBM

Inventor： SIMON ANDREW ,  KWON UNOH ,  LI ZHENGWEN ,  WONG KEITH KWONG HON ,  PAPADATOS FILIPPOS ,  CHUDZIK MICHAEL P

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8238

公开(公告)号：GB2491935A

公开(公告)日：2012-12-19

申请号：GB201208149

申请日：2010-12-09

Applicant: IBM

Inventor： FRYE ASA ,  SIMON ANDREW

IPC: H01L21/285 ,  H01L29/66

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers (105, 106) over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) (100) through a physical vapor deposition (PVD) process, wherein the first metal layer (105) is deposited using a first nickel target material containing platinum (Pt), and the second metal layer (106) is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel- silicide layer (107) at a top surface of the gate, source, and drain regions.

公开(公告)号：GB2490819A

公开(公告)日：2012-11-14

申请号：GB201213193

申请日：2011-02-24

Applicant: IBM

Inventor： SIMON ANDREW ,  KWON UNOH ,  LI ZHENGWEN ,  WONG KEITH KWONG HON ,  PAPADATOS FILIPPOS ,  CHUDZIK MICHAEL P

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8238

Abstract: An electrical device is provided with a p-type semiconductor device (105) having a first gate structure (60) that includes a gate dielectric (10) on top of a semiconductor substrate (5), a p-type work function metal layer (25), a metal layer (28) composed of titanium and aluminum, and a metal fill (29 ) composed of aluminum. An n-type semiconductor device (100) is also present, on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric (30) is present over the semiconductor substrate. The interlevel dielectric includes interconnects (80) to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminium, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.