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    MIM CAPACITOR STRUCTURES AND FABRICATION METHODS IN DUAL-DAMASCENE STRUCTURES
    1.
    发明公开
    MIM CAPACITOR STRUCTURES AND FABRICATION METHODS IN DUAL-DAMASCENE STRUCTURES 有权
    MIM电容器结构和方法，双镶嵌结构

    公开(公告)号：EP1547133A4

    公开(公告)日：2008-11-26

    申请号：EP03754842

    申请日：2003-09-23

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： NING XIAN J ,  WONG KEITH KWONG HON

    IPC: H01L21/02 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/5223 ,  H01L21/31604 ,  H01L21/76807 ,  H01L28/55 ,  H01L28/60 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern having a first pattern (216) and a second pattern (218). The second pattern (218) has a greater depth than the first pattern (216). A conductive layer (226) is formed over the dielectric layer (214) in the first pattern, and a conductive layer is formed over the conductive layer in the first pattern (216). A dielectric layer (232), conductive layer (234), dielectric layer (236) and conductive layer (238) are disposed over the conductive layer (226) of the second pattern (218). Conductive layer (234), dielectric layer (232) and conductive layer (226) form a first MIM capacitor (252). Conductive layer (238), dielectric layer (236) and conductive layer (234) form a second MIM capacitor (242) parallel to the first MIM capacitor (242).

    ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT
    5.
    发明申请
    ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT 审中-公开
    含门槛电压的铝金属门槛

    公开(公告)号：WO2011051015A3

    公开(公告)日：2011-10-20

    申请号：PCT/EP2010062579

    申请日：2010-08-27

    Applicant: IBM ,  IBM UK ,  WONG KEITH KWONG HON ,  GUO DECHAO ,  KWON UNOH ,  WANG YUN-YU ,  PARKS CHRISTOPHER CARR

    Inventor： WONG KEITH KWONG HON ,  GUO DECHAO ,  KWON UNOH ,  WANG YUN-YU ,  PARKS CHRISTOPHER CARR

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

    Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

    Abstract translation: 提供了一种形成p型半导体器件的方法，其在一个实施例中采用含铝阈值电压偏移层来产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极介电层，存在于栅极介电层上的含铝阈值电压偏移层， 以及与含铝阈值电压偏移层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区域可以形成在衬底的与其上存在栅极结构的部分相邻的衬底中。 还提供了由上述方法提供的p型半导体器件。

    METHOD OF MANUFACTURING POLYMER CONDUCTING WIRE AND INTEGRATED CIRCUIT STRUCTURE
    6.
    发明专利
    METHOD OF MANUFACTURING POLYMER CONDUCTING WIRE AND INTEGRATED CIRCUIT STRUCTURE 审中-公开

    公开(公告)号：JP2003133317A

    公开(公告)日：2003-05-09

    申请号：JP2002193642

    申请日：2002-07-02

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  WANG LI-KONG ,  WONG KEITH KWONG HON

    IPC: G03F7/40 ,  H01B13/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H05K3/02

    Abstract: PROBLEM TO BE SOLVED: To provide a more simplified substitutional method of the conventional damascene approach. SOLUTION: The cloisonne approach includes a step of coating a semiconductor substrate with a photosensitive polymer, such as pyrrole having a silver salt, aniline, etc. A conductive polymer is exposed to a wet developing solution, by using standard photolithography and the resists developing method and only conductive polymer wires are left on a substrate by removing part of the exposed conductive polymer region. Then an insulating dielectric layer is adhered to the whole structure, and conductive polymer wires are produced by planarizing an insulator by the chemical mechanical polishing (CMP). Another embodiment of this invention includes a method and structure for a self- planarizing interconnecting material containing the conductive polymer. Consequently, the number of treating steps can be reduced, as compared with the conventional technology.

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