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    instruções para realizar uma operação em dois operandos e subsequentemente armazenar o valor original do operando
    11.
    发明专利
    instruções para realizar uma operação em dois operandos e subsequentemente armazenar o valor original do operando 未知

    公开(公告)号：BRPI1103258A2

    公开(公告)日：2016-01-12

    申请号：BRPI1103258

    申请日：2011-06-22

    Applicant: IBM

    Inventor： GREINER DAN F ,  MITRAM MARCEL ,  SLEGEL TIMOTHY J

    IPC: G06F9/30

    Abstract: instruções para realizar uma operação em dois operando e subsequentemente armazenar o valor original do operando. uma instrução aritmética / lógica é executada com operandos de memória interligados, quando executados obtêm um segundo operando a partir de uma localização na memória, e salva uma cópia temporária do segundo operando, a execução realiza uma operação aritmética ou lógica baseada no segundo operando e um terceiro operando e armazena o resultado na localização de memória do segundo operando, e, posteriormente, armazena a cópia temporária em um primeiro registro.

    Controlling operation of a run-time instrumentation facility from a lesser-privileged state
    15.
    发明专利
    Controlling operation of a run-time instrumentation facility from a lesser-privileged state 未知

    公开(公告)号：AU2013233830A1

    公开(公告)日：2014-09-11

    申请号：AU2013233830

    申请日：2013-03-01

    Applicant: IBM

    Inventor： FARRELL MARK S ,  GAINEY JR CHARLES W ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  SLEGEL TIMOTHY J ,  SMITH BRIAN LEONARD ,  STOODLEY KEVIN A

    IPC: G06F11/34

    Abstract: Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.

    Invalidating storage, clearing buffer entries
    16.
    发明专利
    Invalidating storage, clearing buffer entries 未知

    公开(公告)号：GB2414842B

    公开(公告)日：2006-07-05

    申请号：GB0518904

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY J ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F12/10

    Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

    Clearing specific entries in a buffer
    17.
    发明专利
    Clearing specific entries in a buffer 未知

    公开(公告)号：GB2414842A

    公开(公告)日：2005-12-07

    申请号：GB0518904

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY J ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

    Abstract: Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

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