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    METHOD OF SHARING TRANSLATION LOOKASIDE BUFFER AMONG CPUS
    1.
    发明专利
    METHOD OF SHARING TRANSLATION LOOKASIDE BUFFER AMONG CPUS 审中-公开

    公开(公告)号：JP2002358235A

    公开(公告)日：2002-12-13

    申请号：JP2002115333

    申请日：2002-04-17

    Applicant: IBM

    Inventor： GAERTNER UTE ,  HAGSPIEL NORBERT ,  LEHNERT FRANK ,  PFEFFER ERWIN ,  SCHELM KERSTIN

    IPC: G06F12/1027 ,  G06F12/08 ,  G06F12/10

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a system of sharing a TLB2 among CPUs transparently in the CPU architecture and therefore in compliance with the architecture rule. SOLUTION: This invention, in general, refers to a shared memory multiprocessor system of IBM ESA/390 or RS/6000 system, or the like, and in particular refers to the method and the system that share, among a plurality of CPUs, the translation lookaside buffer(TLB2) of second level to improve the performance and reduce a chip area necessary for buffering the result of virtual/absolute address translation. The invented TLB2 configuration includes a plurality of small arrays dedicated for a specific CPU, thus providing an interface for a main array shared among CPUs. The dedicated array is required to meet systematic restrictions and provide a link to a shared array commonly used by a plurality of CPUs.

    Interrupt handling in a logically partitioned system by changing the interrupt status values in an array for only one partition at a time.
    2.
    发明专利
    Interrupt handling in a logically partitioned system by changing the interrupt status values in an array for only one partition at a time. 未知

    公开(公告)号：GB2454817A

    公开(公告)日：2009-05-20

    申请号：GB0822116

    申请日：2008-12-04

    Applicant: IBM

    Inventor： CAMPBELL MICHAEL ,  EASTON JANET R ,  HAGSPIEL NORBERT ,  SLEGEL TIMOTHY J

    IPC: G06F9/48

    Abstract: Disclosed is a method of interrupt handling in a logically partitioned data processing system. The system has at least two logical partition zones and at least one interrupt handling array, which includes bit values that change in accordance with the change of an interrupt pending status of the data processing system. A change of the interruption pending status is only performed for a logical partition zone having an updated bit value. The interrupt pending status is changed for only one partition at a time. The current interrupt pending status for all the zones may be stored as a vector or array of interrupt states, with one bit per zone. In the cases where a back-to-back writes to the same entry in the array a bypass may be used to bypass the array.

    Data processing apparatus and method
    3.
    发明专利
    Data processing apparatus and method 未知

    公开(公告)号：GB2529425A

    公开(公告)日：2016-02-24

    申请号：GB201414711

    申请日：2014-08-19

    Applicant: IBM

    Inventor： HAGSPIEL NORBERT ,  KLEIN MATTHIAS ,  JUNGHANS SASCHA ,  WALTER JOERG ,  AMBROLADZE ELATEROMA M

    IPC: G06F13/28

    Abstract: A data processing apparatus 1 comprises: a number of processor cores 2a, 2b; a shared processor cache 3 connected to each of the processor cores and to a main memory 6; a bus controller 4 connected to the shared processor cache and configured, in response to receiving a descriptor sent S100, S105, S140 by one of the processor cores, to perform a transfer S155 of requested data indicated by the descriptor from the shared processor cache to an I/O device 7; a bus unit 5 connected to the bus controller and configured for transferring data to/from the I/O device; where the shared processor cache comprises means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access S125 in response to receiving a descriptor from one of the processor cores. The descriptor may comprise address and length information. Efficient data transfer with reduced latency is facilitated.

    Tracing data from an asynchronous interface
    4.
    发明专利
    Tracing data from an asynchronous interface 未知

    公开(公告)号：GB2527108A

    公开(公告)日：2015-12-16

    申请号：GB201410488

    申请日：2014-06-12

    Applicant: IBM

    Inventor： HAGSPIEL NORBERT ,  KLEIN MATTHIAS ,  JUNGHANS SASCHA ,  WALTER JOERG

    IPC: G06F1/12 ,  G06F5/06 ,  G06F11/36 ,  G06F13/14 ,  G06F13/38

    Abstract: Apparatus (10) for tracing data (24) from a data bus (20) in a first clock domain (12) operating at a first clock frequency (14) to a trace array (22) in a second clock domain (16) operating at a second clock frequency (18), wherein the first clock frequency is lower than the second clock frequency. The apparatus comprises; (i) change detector means (26) to detect a change of the data on the data bus in the first clock domain, (ii) trigger means (28) responsive to the change detector means (26) to send a trigger pulse (34) to the second clock domain, (iii) pulse synchronization means (30) on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch (36), and (iv) data capture means (32) in the second clock domain responsive to the pulse synchronization means to capture data from the data bus and to store the captured data (25) in the trace array.

    Data processing apparatus and method
    5.
    发明专利
    Data processing apparatus and method 未知

    公开(公告)号：GB2520729A

    公开(公告)日：2015-06-03

    申请号：GB201321069

    申请日：2013-11-29

    Applicant: IBM

    Inventor： HAGSPIEL NORBERT ,  KLEIN MATTHIAS ,  WALTER JOERG ,  JUNGHANS SASCHA

    IPC: G06F13/28 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0871

    Abstract: In computer system operation overall system performance may strongly suffer from limitations in the rate of data transfer from the processor to I/O devices. In particular, this applies to a data processing apparatus comprising a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring of data to/from an I/O device. The bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit. The data transfer between the processor cache and I/O devices is managed by the bus controller independent of the processor cores. The descriptor may be created by a processor core and transferred to the bus controller after being written to the shared processor cache by the processor core. The bus controller may fetch data from the main memory to the shared processor cache.

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