公开(公告)号：AU2176277A

公开(公告)日：1978-08-03

申请号：AU2176277

申请日：1977-01-28

Applicant: IBM

Inventor： HELLER LAWRENCE GRIFFITH ,  SPAMPINATO DOMINIC PATRICK

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03F3/45 ,  H03K3/356

公开(公告)号：DE2620973A1

公开(公告)日：1977-01-27

申请号：DE2620973

申请日：1976-05-12

Applicant: IBM

Inventor： SPAMPINATO DOMINIC PATRICK ,  TERMAN LEWIS MADISON

IPC: G11C11/401 ,  G05F3/20 ,  G11C11/35 ,  G11C19/28 ,  H01L21/822 ,  H01L27/04 ,  H01L29/768 ,  H03K19/096 ,  H01L23/56

公开(公告)号：DE2225428A1

公开(公告)日：1973-01-11

申请号：DE2225428

申请日：1972-05-25

Applicant: IBM

Inventor： PARRISH JAMES THOMAS ,  SPAMPINATO DOMINIC PATRICK ,  TERMAN LEWIS MADISON

IPC: G11C19/18 ,  G11C19/28 ,  H03K19/096 ,  G11C19/00

Abstract: An inverter incorporating a pair of complementary field effect transistors and a pair of Schottky barrier diodes disposed in series with the complementary transistors is disclosed. The gates of the complementary transistors are connected in parallel to a pulsed source which provides positive and negative inputs to the inverter. First and second pulsed sources are connected to the inverter which, during an ENABLE cycle, provide voltages of opposite polarity to the inverter which, operating in a common source mode, charges an output to one of the source potentials. During a DISABLE cycle, the potential at the output is locked at a node by applying to the inverter potentials complementary to those initially applied to the inverter. A shift register stage consisting of the arrangement just described and an inverted inverter is also disclosed. When this shift register stage is actuated, during the ENABLE portion of a given cycle, one inverter is enabled while the other is disabled and, during the DISABLE portion of the given cycle, the other inverter is enabled while the first inverter is disabled. Also included are embodiments which are operable in a static mode as well as a cynamic mode.