公开(公告)号：DE2711829A1

公开(公告)日：1977-10-13

申请号：DE2711829

申请日：1977-03-18

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  PARRISH JAMES THOMAS ,  SCHUSTER STANLEY EVERETT

IPC: H03M1/10 ,  H03K5/08 ,  H03M1/00 ,  H03M1/38 ,  H03K13/05

Abstract: A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement. The other electrode of both the third and fourth FETs are connected to a common phase voltage source. An offset voltage is generated at the input to either of the gate electrodes of the first and second FETs to set the comparator at a balance point and thereby compensate for the differences in the threshold voltages and current carrying capabilities of the four FETs. Also, the comparator has relatively high input impedance, gain and bandwidth.

公开(公告)号：DE2225428A1

公开(公告)日：1973-01-11

申请号：DE2225428

申请日：1972-05-25

Applicant: IBM

Inventor： PARRISH JAMES THOMAS ,  SPAMPINATO DOMINIC PATRICK ,  TERMAN LEWIS MADISON

IPC: G11C19/18 ,  G11C19/28 ,  H03K19/096 ,  G11C19/00

Abstract: An inverter incorporating a pair of complementary field effect transistors and a pair of Schottky barrier diodes disposed in series with the complementary transistors is disclosed. The gates of the complementary transistors are connected in parallel to a pulsed source which provides positive and negative inputs to the inverter. First and second pulsed sources are connected to the inverter which, during an ENABLE cycle, provide voltages of opposite polarity to the inverter which, operating in a common source mode, charges an output to one of the source potentials. During a DISABLE cycle, the potential at the output is locked at a node by applying to the inverter potentials complementary to those initially applied to the inverter. A shift register stage consisting of the arrangement just described and an inverted inverter is also disclosed. When this shift register stage is actuated, during the ENABLE portion of a given cycle, one inverter is enabled while the other is disabled and, during the DISABLE portion of the given cycle, the other inverter is enabled while the first inverter is disabled. Also included are embodiments which are operable in a static mode as well as a cynamic mode.