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    2.
    发明专利
    未知

    公开(公告)号：CH594956A5

    公开(公告)日：1978-01-31

    申请号：CH670475

    申请日：1975-05-26

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  SPAMPINATO DOMINIC PATRICK

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70 ,  G11C11/34 ,  G11C5/02

    Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

    3.
    发明专利
    未知

    公开(公告)号：DE2725613A1

    公开(公告)日：1977-12-29

    申请号：DE2725613

    申请日：1977-06-07

    Applicant: IBM DEUTSCHLAND

    Inventor： MIERSCH EKKEHARD FRITZ DIPL PH ,  SPAMPINATO DOMINIC PATRICK

    IPC: G11C11/405 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/24

    Abstract: 1523094 Transistor memory cells INTERNATIONAL BUSINESS MACHINES CORP 25 April 1977 [17 June 1976] 17190/77 Heading H3T A memory cell comprises a single storage capacitor C, coupled in a series circuit including the source-drain paths of two FET's 1, 3 between two bit/sense lines B/S0, B/S1, the gate electrodes of the two transistors being coupled to the word line. The cell provides a differential signal and obviates the need for a dummy cell to provide a reference signal for detecting the cell state. To write data into the cell, the transistors 1,3 are turned on to allow capacitor C s to charge in one sense or the other, depending on whether a "0" or a " 1" is being written in. The transistors are then turned off to leave the capacitor floating. To read, the transistors are again turned on, and the differential voltage across the capacitor is sensed between the bit/sense lines.

    6.
    发明专利
    未知

    公开(公告)号：DE2708702A1

    公开(公告)日：1977-09-15

    申请号：DE2708702

    申请日：1977-03-01

    Applicant: IBM

    Inventor： SPAMPINATO DOMINIC PATRICK

    IPC: G11C11/41 ,  G11C8/08 ,  G11C8/10 ,  G11C11/407 ,  G11C11/413 ,  G11C7/00

    Abstract: WORD LINE CLAMPING CIRCUIT of the Invention A word line clamping circuit for use with field effect transistor memories is disclosed which permits the clamping of the word line to a reference potential using a minimum of devices and without the consumption of d.c. power so that multi-level bit line potentials may be utilized during the memory cycle. This is achieved by connecting a field effect transistor (FET) between word line and ground under control of a word line decoder so that a node associated with the last mentioned FET is held in either an uncharged or charged condition depending on whether the decoder is selecting its associated word line or not selecting it. Because the unselected word lines are held at ground during a portion of the memory cycle when reading or writing of memory cells associated with a selected word line is taking place, any capacitive coupling which might change the content of cells associated with unselected word lines is avoided and, for whatever the reason, bit line potentials may now be changed to different levels without affecting information storage during the memory cycle. Two circuits are shown which, under control of the word line decoder, permit the grounding of unselected word lines during at least a major portion of the memory cycle.

    8.
    发明专利
    未知

    公开(公告)号：DE2525225A1

    公开(公告)日：1976-02-05

    申请号：DE2525225

    申请日：1975-06-06

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  SPAMPINATO DOMINIC PATRICK

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70

    Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

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