公开(公告)号：AU2003298240A8

公开(公告)日：2004-06-23

申请号：AU2003298240

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：JP2008097598A

公开(公告)日：2008-04-24

申请号：JP2007247897

申请日：2007-09-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN ,  DEREK EDWARD WILLIAMS ,  WILLIAMS PHILLIP G

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0817

Abstract: PROBLEM TO BE SOLVED: To provide an improved processing unit and a data processing system and method for coherency management in a multiprocessor data processing system.
SOLUTION: A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. The method of data processing includes a step for buffering a cache line in a data array of the cache memory and a step for setting a state field in a cache directory of the cache memory to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in the second coherency domain may hold a copy of the cache line.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种改进的处理单元和用于多处理器数据处理系统中的一致性管理的数据处理系统和方法。 解决方案：多处理器数据处理系统至少包括第一和第二相干域，其中第一相干域包括系统存储器和高速缓冲存储器。 数据处理方法包括缓存高速缓冲存储器的数据阵列中的高速缓存行的步骤，以及将高速缓冲存储器的高速缓存目录中的状态字段设置为一致性状态以指示高速缓存行有效的步骤 所述数据阵列，所述高速缓存行被非排他地保存在所述高速缓冲存储器中，并且所述第二相关域中的另一个高速缓冲存储器可以保存所述高速缓存行的副本。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008077650A

公开(公告)日：2008-04-03

申请号：JP2007233730

申请日：2007-09-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN ,  DEREK EDWARD WILLIAMS ,  JAMES S FIELDS JR

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815

Abstract: PROBLEM TO BE SOLVED: To provide a processor, data processing system and data processing method for supporting improved coherency management about castouts in cache coherency of the data processing system. SOLUTION: The method of coherency management in a data processing system includes the steps for: holding a cache line in an upper level cache memory in an exclusive ownership coherency state; thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line including an indication of a shared ownership coherency state from the upper level cache memory to a lower level cache memory; and placing the cache line, in response to the castout request, in the lower level cache memory in a coherency state determined in accordance with the castout request. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种处理器，数据处理系统和数据处理方法，用于支持关于数据处理系统的高速缓存一致性中关于castout的改进的一致性管理。 解决方案：数据处理系统中的一致性管理方法包括以下步骤：在独占所有权一致性状态下将高速缓存行保持在上级高速缓冲存储器中; 然后从高级缓存存储器中移除高速缓存线，并且向高速缓存存储器发送包含共享所有权一致性状态的指示的高速缓存行的转换请求; 以及响应于所述转储请求，将所述高速缓存行放置在根据所述转储请求确定的一致性状态的所述较低级高速缓冲存储器中。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007080266A

公开(公告)日：2007-03-29

申请号：JP2006243808

申请日：2006-09-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FIELDS JAMES S JR ,  STARKE WILLIAM JOHN ,  STUECHELI JEFFREY A ,  GUY LYNN GUTHRIE ,  DALY GEORGE W JR

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0811

Abstract: PROBLEM TO BE SOLVED: To provide a data processing method in a cache coherent data processing system. SOLUTION: A data processing system includes at least a first processing node including an I/O controller and a second processing node including a memory controller for a memory. The memory controller receives pipelined first and second DMA write operations targeting first and second addresses in order from the I/O controller. In response to the second DMA write operation, the status of a domain symbol relating to the second address is established, and an operation scope including the first processing node is indicated. In response to the memory controller receiving a data access request specifying the second adress and having a scope excluding the first processing node, on the basis of the status of the domain symbol relating to the second address, a data access request is forcibly issued again with the scope including the first processing node. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：在高速缓存一致性数据处理系统中提供数据处理方法。 解决方案：数据处理系统至少包括包括I / O控制器的第一处理节点和包括用于存储器的存储器控​​制器的第二处理节点。 存储器控制器从I / O控制器按顺序接收针对第一和第二地址的流水线的第一和第二DMA写操作。 响应于第二DMA写入操作，建立与第二地址有关的域符号的状态，并且指示包括第一处理节点的操作范围。 响应于存储器控制器接收到指定第二地址的数据访问请求并且具有排除第一处理节点的范围，基于与第二地址相关的域符号的状态，再次强制地发送数据访问请求， 范围包括第一个处理节点。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004220581A

公开(公告)日：2004-08-05

申请号：JP2003421698

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F12/08 ,  G06F3/00 ,  G06F12/02 ,  G06F12/10 ,  G06F13/12 ,  G06F13/14

CPC classification number: G06F13/124 ,  G06F12/0835

Abstract: PROBLEM TO BE SOLVED: To provide an improved processor, a data processing system and a data processing method. SOLUTION: An integrated circuit such as the processor includes a substrate and an integrated circuit element formed in the substrate. The integrated circuit element includes a processor core executing an instruction, an interconnect interface coupled to the processor core and supporting a communication between the processor core and a system interconnect external to the integrated circuit and, at least, a part of an external communication adapter coupled to the processor core and supporting input/output communication via an input/output communication link. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供改进的处理器，数据处理系统和数据处理方法。 解决方案：诸如处理器的集成电路包括衬底和形成在衬底中的集成电路元件。 集成电路元件包括执行指令的处理器核心，耦合到处理器核心的互连接口，并且支持处理器核心与集成电路外部的系统互连之间的通信，并且至少部分外部通信适配器耦合 到处理器核心并通过输入/输出通信链路支持输入/输出通信。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004185604A

公开(公告)日：2004-07-02

申请号：JP2003368033

申请日：2003-10-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAVI KUMER ARIMIRRI ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0831

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for minimizing a delay when processing an interruption. SOLUTION: This method and system are for managing stored software state information such as cache memory contents and address conversion information which are not important for executing a process inside a processor. The software state of an idle process is stored in a virtual cache inside a system memory. By snooping a kill-type operation for the virtual cache inside the system memory, the cache coherency of the software state in maintained. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在处理中断时使延迟最小化的方法和系统。 解决方案：该方法和系统用于管理存储的软件状态信息，例如高速缓存存储器内容和地址转换信息，这些信息对于在处理器内执行处理不重要。 空闲进程的软件状态存储在系统内存中的虚拟缓存中。 通过窥探系统内存中的虚拟缓存的kill-type操作，维护软件状态的高速缓存一致性。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004185603A

公开(公告)日：2004-07-02

申请号：JP2003368019

申请日：2003-10-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAVI KUMER ARIMIRRI ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/32 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/3863 ,  G06F9/30101 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/4812

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for minimizing a delay when processing an interruption. SOLUTION: This method and system are for predicting a second level interruption handler (SLIH) for processing then interruption on the basis of history information. The predicted SLIH is speculatively executed at the same time as a first level interruption handler (FLIH) for determining a right SLIH for interruption. When the predicted SLIH is rightly predicted, the FLIH suspends execution of the SLIH called by the FLIH, and the predicted SLIH completes the execution. When the predicted SLIH is wrongly predicted, the execution of the predicted SLIH is suspended, and the SLIH called by the FLIH continues till the completion. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：CA2508041C

公开(公告)日：2011-06-07

申请号：CA2508041

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：CA2508551C

公开(公告)日：2008-12-16

申请号：CA2508551

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  GUTHRIE GUY LYNN ,  CARGNONI ROBERT ALAN

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/02

Abstract: A method and system are disclosed for saving soft state information, which i s non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memor y associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan - chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

公开(公告)号：AU2003302510A1

公开(公告)日：2004-06-23

申请号：AU2003302510

申请日：2003-11-14

Applicant: IBM

Inventor： CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN ,  ARIMILLI RAVI KUMAR

IPC: G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.