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    WRITE-DRIVER OF DRAM
    11.
    发明专利
    WRITE-DRIVER OF DRAM 失效

    公开(公告)号：JP2002298581A

    公开(公告)日：2002-10-11

    申请号：JP2001098160

    申请日：2001-03-30

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  HOSOKAWA KOJI

    IPC: G11C11/409 ,  G11C11/407

    Abstract: PROBLEM TO BE SOLVED: To provide a write-driver of a DRAM in which operation speed of a write-in cycle of a DRAM is increased, erroneous write-in for a cell not to be written is prevented, and which performs stable write-in. SOLUTION: This write-driver of a DRAM 10 comprises nMOSFET 16c, 16d in which a signal indicating write-in of '1' or '0' is inputted to a gate and data line is connected to a drain, pMOSFET 14c, 14d in which a signal indicating pre-charge of a sense amplifier is inputted to a gate, a power source is connected to a source, and drains are connected to sources of the nMOSFET 16c, 16d, and capacitors Cw0, Cw1 in which sources of the nMOSFET 16c, 16d and drains of the pMOSFET 14c, 14d are connected to ground.

    DRAM, AND REFRESHING METHOD FOR DRAM
    12.
    发明专利
    DRAM, AND REFRESHING METHOD FOR DRAM 失效

    公开(公告)号：JP2002298574A

    公开(公告)日：2002-10-11

    申请号：JP2001095399

    申请日：2001-03-29

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

    IPC: G11C11/403 ,  G11C11/406

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM and a refreshing method performing successively normal access and refreshing in one operation cycle of a SRAM. SOLUTION: A DRAM 10 comprises an execution instruction means instructing execution of refreshing, an address specifying means specifying a row address of a memory cell to be refreshed, and an execution means refreshing a memory cell of a row address specified by the address specifying means when execution of refreshing is instructed from the execution instruction means.

    MEMORY CHIP AND DATA STORAGE METHOD
    13.
    发明专利
    MEMORY CHIP AND DATA STORAGE METHOD 失效

    公开(公告)号：JP2001243771A

    公开(公告)日：2001-09-07

    申请号：JP2000050412

    申请日：2000-02-28

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO

    IPC: G11C11/407 ,  G06F12/02 ,  G06F12/06 ,  G06T1/60 ,  G09G5/39 ,  G09G5/395 ,  G11C11/401

    Abstract: PROBLEM TO BE SOLVED: To execute accessing to various pieces of the image data stored in a memory. SOLUTION: A memory chip 10 is constituted by providing the same with data input/outputs(I/Os) divided to plural blocks, memory arrays (blocks A, B, C and D) where the data input from the respective blocks of the I/Os and the data outputted to the respective blocks are respectively stored and which are divided to the blocks of the sama number as the number of the I/Os and address inputs which assign the addresses for accessing the memory arrays by each of the respective blocks and are divided to the blocks of the same number as the number of the memory arrays.

    DRAM ARRAY
    14.
    发明专利
    DRAM ARRAY 失效

    公开(公告)号：JPH09139075A

    公开(公告)日：1997-05-27

    申请号：JP28384995

    申请日：1995-10-31

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  HOSOKAWA KOJI

    IPC: G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To simultaneously accelerate RAS access time and a data transfer rate for the acceleration of a DRAM. SOLUTION: This DRAM array is provided with a row decoder means 2 and a column decoder means 3 respectively connected to the word line and bit line of a cell matrix part 1 and the column decoder means 3 is provided with plural bit switches 44 and 46 for connecting a prescribed bit line to an output bus and a local latch 36 for storing data bits provided in each group 32 of the bit lines which is the unit of the prescribed number of the bit lines. The bit switch is provided with a hierarchical structure, and since the bit line and the output bus are connected through the two serially connected bit switches, the load capacity of data lines 52 and 56 is reduced. Data inside the respective local latches 36 are serially stored in a local buffer 74 in a prescribed order and fast burst transfer is made possible.

    TRANSFER SYSTEM OF DRAM
    15.
    发明专利
    TRANSFER SYSTEM OF DRAM 失效

    公开(公告)号：JPH08195077A

    公开(公告)日：1996-07-30

    申请号：JP2219495

    申请日：1995-01-17

    Applicant: IBM

    Inventor： FURUTA MINORU ,  SUNANAGA TOSHIO

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407

    Abstract: PURPOSE: To make it possible to continue the burst transmission in the same page while altering a column address by controlling the falling timing of OE. CONSTITUTION: When OE falls 110 and CAS continuously falls 112 at a time t10, burst transmission starting conditions are satisfied. A column address Cay2 is latched at the fall 112, an object to be accessed is decided. The data burst transmission is started from the CAS fall 114 of a time t11, fall data Dy2 is latched, and then data Dy3, 0, 1 are latched at the falls 115, 116, 122 of the CAS. The OE fall 120 and CAS fall 122 are combined as a burst transmission initiation start signal. At the fall 122, next column address CAz3 is latched, and 4 data after the data Dz3 is burst transmitted in response to the CAS fall 124 of time t15 up to time t16 to 19. Accordingly, at the burst initiation start, 4-continuous bit data are always read.

    DRAM CELL
    16.
    发明专利
    DRAM CELL 失效

    公开(公告)号：JPH0765573A

    公开(公告)日：1995-03-10

    申请号：JP16261593

    申请日：1993-06-30

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO

    IPC: G11C11/404 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    Abstract: PURPOSE: To increase a storage voltage and reading signal by connecting a capacitor for a charge pump with a memory cell. CONSTITUTION: A lead 24, which works as a charge pump control line UP, is installed on a word line 22. The lead 24 is extending along the word line, and has an extending part 25 which is at least partly overlapped with a trench lead 14 The conductor part 25 is separated from the trench conductor 14 and a connection body 21 by an insulation layer 23, and forms capacitance Cp for the charge pump. The lead 24 has a conductor 25 extending into the trench and the conductor can also be provided so as to form a capacity Cp with the trench conductor 14. In this case, a Cp value can be increased. The capacity Cp and the charge pump control line UP are added to one transistor DRAM cell. A circuit is comprised of a sense amplifier driven by a word line WL, a bit pair BLT and BLC, a cell capacity Cp , a PMOS type charge transport central FETTx, SP, and SN. It is possible to reduce a voltage of a node Nc lower than a threshold voltage of Tx by a temporarily charged voltage of Cp .

    Memory and memory access control method
    17.
    发明专利
    Memory and memory access control method 有权
    存储器和存储器访问控制方法

    公开(公告)号：JP2007095146A

    公开(公告)日：2007-04-12

    申请号：JP2005281687

    申请日：2005-09-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： SUNANAGA TOSHIO ,  MIYATAKE HISATADA

    IPC: G11C11/407 ,  G11C11/403

    CPC classification number: G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076

    Abstract: PROBLEM TO BE SOLVED: To increase a data rate in the data I/O of continuous burst data in a memory. SOLUTION: A memory array, and an access control circuit for controlling access to the memory array are provided. The access control circuit includes an access command circuit (ADRCTL) for receiving first (CE) and second (ADV) input signals to output an access command signal (ACMDS) for notifying memory access, and a command identification circuit (CMDDEC) for receiving the first (CE) and second (ADV) input signals, third (OE) and fourth (WE) input signals, and a clock signal (CLK) to output a command identification signal (WRITE) for specifying the type of an access command signal. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：增加存储器中连续脉冲串数据的数据I / O中的数据速率。 提供了一种用于控制对存储器阵列的访问的存储器阵列和访问控制电路。 访问控制电路包括用于接收第一（CE）和第二（ADV）输入信号以访问用于通知存储器访问的访问命令信号（ACMDS）的访问命令电路（ADRCTL），以及用于接收 第一（CE）和第二（ADV）输入信号，第三（OE）和第四（WE）输入信号，以及时钟信号（CLK），输出用于指定访问命令信号的类型的命令识别信号（WRITE）。 版权所有（C）2007，JPO＆INPIT

    Oscillator
    18.
    发明专利
    Oscillator 有权
    振荡器

    公开(公告)号：JP2005130302A

    公开(公告)日：2005-05-19

    申请号：JP2003365224

    申请日：2003-10-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： YASUDA TAKAO ,  SUNANAGA TOSHIO

    IPC: H03K3/353 ,  G11C11/406 ,  H03K3/0231

    CPC classification number: H03K3/0231

    Abstract: PROBLEM TO BE SOLVED: To provide an oscillator used for semiconductor memories and capable of reducing power consumption.
    SOLUTION: When the voltage V1 of a comparison node N1 becomes larger than a first reference voltage Vref1, a differential amplifier 101 inside the oscillator 1 makes a pulse generating circuit 110 output pulses. When the pulses are output, the comparison node N1 is discharged by a charging/discharging circuit 105. At this point, a control circuit 4 inactivates a first control signal CT1 and stops the differential amplifier 101. After the comparison node N1 is discharged, it is gradually charged by the charging/discharging circuit 105. As a result, when the voltage V1 exceeds a second reference voltage Vref2 which is the total of threshold voltages of a discharging circuit 43, the control circuit 4 activates the first control signal CT1 and operates the differential amplifier 101.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于半导体存储器并能够降低功耗的振荡器。 解决方案：当比较节点N1的电压V1变得大于第一参考电压Vref1时，振荡器1内的差分放大器101使脉冲发生电路110输出脉冲。 当脉冲输出时，比较节点N1由充电/放电电路105放电。此时，控制电路4使第一控制信号CT1失效，并停止差分放大器101.在比较节点N1被放电之后 由充电/放电电路105逐渐充电。结果，当电压V1超过作为放电电路43的阈值电压的总和的第二参考电压Vref2时，控制电路4激活第一控制信号CT1并操作 差分放大器101.版权所有（C）2005，JPO＆NCIPI

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