公开(公告)号：JP2007200319A

公开(公告)日：2007-08-09

申请号：JP2007007741

申请日：2007-01-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RENATO J RECIO ,  STEVEN WADE HUNTER ,  BOYD WILLIAM TODD ,  THURBER STEVE MARK ,  MADELINE VEGA ,  HOLLAND WILLIAM G ,  FREIMUTH DOUGLAS M

IPC: G06F13/00 ,  G06F11/30 ,  G06F13/38

CPC classification number: G06F11/0784 ,  G06F11/0712 ,  G06F11/0724

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus, and computer program for defining to an I/O fabric whether or not any host node and I/O fabric device can be affected by a specific error and transmitting an error message to only a host node affected by the error.
SOLUTION: In a data processing environment including a plurality of host computer system sharing a plurality of devices by making use of the fabric, the error is detected at one device. A route designation table memorized in the fabric device in its fabric is used to discriminate the host computer system affected by the error among the host computer systems. The error message discriminating the error is routed to the discriminated host computer system among the host computer systems.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于定义I / O结构的方法，装置和计算机程序，无论任何主机节点和I / O结构设备是否可能受到特定错误的影响并发送错误消息 仅限于受该错误影响的主机节点。 解决方案：在包括通过使用该结构共享多个设备的多个主机计算机系统的数据处理环境中，在一个设备处检测到错误。 存储在其结构中的结构设备中的路由指定表用于区分受主机计算机系统之间的错误影响的主计算机系统。 区分错误的错误消息被路由到主机计算机系统中的被鉴别主机计算机系统。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH1049482A

公开(公告)日：1998-02-20

申请号：JP8420597

申请日：1997-04-02

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To efficiently process mixed transactions by connecting a 1st secondary bus and a 2nd secondary bus and connecting a bridge to a system bus which generates one logical bus supporting more peripheral devices than a previously set number. SOLUTION: A system 10 connects one host processor 12 to the 1st secondary bus 14 like a system bus that supports many peripheral devices which can be used by a multiprocessor system and also connects the other host processor 12 to the 1st secondary bus 14. Then the host bridge 20A is connected to the 1st secondary bus 14 and the 1st secondary bus 14 and 2nd secondary bus 16 are connected to each other. Further, a system memory 15 is connected to the 1st secondary bus 14 and 30 and 40 as other devices are connected to the 2nd secondary bus 16. Consequently, mixed transactions of the host bridge 20A can efficiently be processed.

公开(公告)号：DE69736872D1

公开(公告)日：2006-12-14

申请号：DE69736872

申请日：1997-03-20

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/40 ,  G06F13/36

Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.